Abstract: The present invention relates to nucleoside derivatives represented by general formulas I and II, their synthetic methods and their pharmacologically acceptable salts thereof, and compositions containing such compounds. Methods for treating hyperproliferative disorders by administering the compounds are also included.

Abstract: The present invention provides a battery having a structure for increasing the power storage capacity and output thereof In accordance with the present invention, in a battery comprising an electrode assembly including anode plates, cathode plates and separators; and a battery case, both side bonding portions of which are folded toward adjacent sides thereof, for accommodating the electrode assembly and a designated amount of electrolyte, and sealing the electrode assembly such that two electrode terminals connected to corresponding electrode taps of the anode and cathode plates of the electrode assembly are exposed to the outside, an upper bonding portion of the battery case is folded toward the upper end of the battery case, and/or common portions of the upper bonding portion and both side portions of the battery case are cut off, and/or inner corners corresponding to the upper bonding portion have larger radiuses of curvature, and/or receipt portions for receiving the electrode assembly are respectively fo

Abstract: Quinazoline derivatives represented by the general formula pharmacologically acceptable salts thereof, and compositions containing such compounds are described. Methods for using the compounds for treatment of hyperproliferative disorders are also described.

Abstract: Provided is a cell wherein out of electrodes constituting the cell, the outermost two electrodes are both cathodes, cathode current collectors of the cathodes are single-side coated with cathode active materials on the first surfaces thereof, other sides of cathode current collectors non-coated with cathode active materials are disposed toward the outside of a cell assembly and the thickness of cathode current collectors is 70 to 150% of that of the cathode active material coated layer. The cell in accordance with the present invention exhibits excellent safety in a nail penetration test.

Abstract: A semiconductor memory test apparatus includes a test signal input unit for externally receiving a test word line model signal and a test column address pulse enable signal, which are used for a memory operation in the test mode. The test apparatus also includes a test mode setting unit that receives: a row address strobe bar signal, a column address strobe bar signal, a write enable bar signal and an address signal, and that generates first and second test mode setting signals. A first switching unit switches a signal input from a row address path circuit or from the test signal input unit, in accordance with a first test mode setting signal. A second switching unit switches another signal input from the row address path circuit or from the test signal input unit in accordance with a second test mode setting signal, and outputs the switched signal to the column address path circuit.

Abstract: A semiconductor memory apparatus having a refresh test circuit provided with a control unit, a write control unit, a row address buffer and column address buffer, a refresh address counter, a refresh control unit, a column decoder, a data input/output buffer, a plurality of sense amplifier arrays and a plurality of memory cell arrays, includes a refresh test control unit for receiving an address signal by the control of the control unit and controlling the refresh control unit, the row block decoder and the plurality of sense amplifier arrays. The apparatus screens refresh-related poor products by efficiently applying a disturb refresh test during a short period of time.

Abstract: A redundancy circuit for a semiconductor integrated circuit is disclosed, which includes each cell of the column redundancy cell block corresponding to each cell of the cell sub-array is connected opposite to the connection of the cells of the cell sub-array, wherein a state that an electric charge corresponding to a data written into each cell of the cell sub-array and the column redundancy cell block is discharged, is measured for thus accurately checking the position of the repaired cell after the redundancy operation is performed.

Abstract: A test apparatus for a semi-conductor memory device comprising a memory section having a plurality of memory cell arrays, the memory cell arrays receiving input data in parallel, a latch control circuit responsive to a write enable signal and an address signal for outputting a control signal for latching the input data while the input data is written into the memory section, an expected data latch circuit responsive to the control signal from the latch control circuit and a read enable signal for latching the input data while the input data is written into the memory section and outputting the resultant expected data, a clock generator for generating a clock signal in response to a test flag signal and an internal column address select signal, an expected data transfer circuit for transferring the expected data from the expected data latch circuit in response to the test enable signal and the read enable signal, a data discrimination circuit for discriminating whether output data from the memory section are t

Abstract: The present invention relates to a novel 2-aminothiazolecarboxamide derivative represented by the following general formula (I): ##STR1## in which R.sup.1 -R.sup.5 are defined herein, which is a fungicidal agent useful for controlling phytopathogenic organisms. In addition, the present invention also relates to a process for preparing the novel 2-aminothiazolecarboxamide derivative of formula (I) and use of the compound of formula (I) as an agent for controlling phytopathogenic organisms.