Abstract: A quick-release device for a crossbow stock assembly includes a main body having a fixing member which is threadedly connected to the extension of the stock. An axial groove is defined in the outside of the threaded section of the extension. A locking member is pivotably connected to the fixing member and positioned between a locked position and a release position. The locking member has an engaging end and a press end. The engaging end is engaged with the axial groove when the locking member is located at the locked position, and the engaging end is separated from the axial groove when the locking member is located at the release position. A collar is threadedly connected to the threaded section to keep the locking member at the locked position. The stock is quickly installed to or removed from the main body of the crossbow.

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: A method includes creating an opening in a dielectric layer that is disposed over a bottom electrode layer. A top electrode layer is disposed over the dielectric layer. A magnetic tunnel junction (MTJ) layer is formed in the opening over the bottom electrode layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.

Abstract: The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

Abstract: A first device in a network, having a first port, receives an identifier of a second port of a second device in the network, the network comprising a host entity, a switch, and a storage system. The first port of the first device spoofs the second port of the second device, during a communication with the switch. The first device receives information identifying a third port of a third device in the network that is zoned to the second port of the second device. The device identifies data stored in the storage system that may be accessed by the host entity, based at least on the information.

Abstract: An image processing system, and a method of operation thereof, including: a feature selection module for determining subsets of point clouds, the subsets selected based on key points of a three-dimensional object; a feature matching module, coupled to the feature selection module, for generating matched results based on a matching transformation of the subsets; and a point registration module, coupled to the feature matching module, for refining the matched results based on a refinement transformation to optionally align different data sets of the point clouds for displaying the aligned data sets on a device, wherein the refinement transformation includes a refinement error less than a matching error of the matching transformation.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming an MRAM device, and a method of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a second layer over a first layer, and performing a first etch process on the second layer to define a feature, wherein the first etch process forms a film on a surface of the feature. The method further comprises performing an ion beam etch process on the feature, wherein the ion beam etch removes the film from the surface of the feature.

Abstract: A memory card with a smart card function including a flash memory unit, a data processing control unit, and a power control unit is provided. The data processing control unit is coupled to the flash memory unit. The data processing control unit controls the flash memory unit and encrypts, decrypts and stores smart card security data. The power control unit receives at least one of a first power input and a second power input. The power control unit selects the first power input or the second power input and provides the selected one to the data processing control unit according to at least one control signal. An output terminal of the power control unit is coupled to the first power input. Furthermore, a power control method and a power control circuit of the forgoing memory card are also provided.

Abstract: It discloses a vanadium-titanium compound material with high thermal stability and high activity and a preparation method thereof. The vanadium-titanium compound material is mainly composed of vanadium oxide and titanium oxide, where the content of vanadium oxide is 0.5% to 30% by mass of the vanadium-titanium compound material, and the crystal form of titanium oxide in the vanadium-titanium compound material is one of anatase and TiO2(B) or a mixture thereof.

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract: In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer.

Abstract: Semiconductor structures are presented. An exemplary semiconductor structure comprises a common source region having a sawtooth profile, and a flat erase gate disposed above the common source region. Methods of making semiconductor structures are also presented. An exemplary method comprises forming a plurality of trenches in a substrate thereby forming a plurality of active regions; forming a common source region in the substrate in a direction perpendicular to the active regions. The exemplary method further comprises, after forming the common source region, forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features, and forming an erase gate on the dielectric feature.

Abstract: A touch panel including sensing electrode sets, first pads, second pads, first conductive lines, second conductive lines and resistors is provided. Each sensing electrode set includes a first sensing electrode pattern and second sensing electrode patterns disposed beside the first sensing electrode pattern. The first conductive lines electrically connect the first sensing electrode pattern with the first pads respectively. The second conductive lines connect the second electrode patterns into multiple series. The second sensing electrode patterns of the same sensing electrode set belong to different series and two terminals of each series are connected to different second pads. Two terminals of each resistor are connected to the different second pads connected with the two terminals of the each series.

Abstract: The present invention provides a method and apparatus reporting a channel quality indicator (CQI) of a communication system, including: detecting a first measurement reflecting a first communication quality of the communication system, providing first reference(s) respectively corresponding to indicator level(s), providing CQI according to the indicator level(s) and a relation between the first measurement and the first reference(s), and updating one (or more) first reference according to a second measurement reflecting a second communication quality of the communication system. For example, the first measurement can represent signal to interference ratio or mutual information, and the second measurement can represent data error rate or throughput. First reference(s) can be further adjusted according to a third measurement, e.g., a power scheduling of base station, such that CQI can be updated if base station schedules additional transmission power.

Abstract: The present disclosure disclosed a light-emitting device with thin film transistors, comprising: a substrate and a substrate insulating layer formed thereon; a gate electrode, a source electrode, and a drain electrode. The gate electrode is arranged on the substrate insulating layer, and a gate insulating layer is formed between the gate electrode and the electrodes of the source and the drain. An oxide semiconductor layer comprises a resource region and a drain region being in electric contact with the source electrode and the drain electrode respectively and a channel region for providing a conductive channel therebetween. A passivation layer is arranged on a part of the gate insulating layer, the source electrode, the drain electrode, and the oxide semiconductor layer. A shielding layer is arranged on the passivation layer for shielding the external light from illuminating on the oxide semiconductor layer. The present device can increase the conductive performance and stability of the component.