Patents by Inventor Chang An Yang

Chang An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071294
    Abstract: A light emitting display device includes a substrate, a drive power circuit, a gate circuit unit, multiple LEDs and a power switch unit. The power switch unit includes multiple first transistor switches and at least one second transistor switch that cooperatively control current flows through the LEDs. The first transistor switches are respectively connected to first terminals of the LEDs. The at least one second transistor switch is connected to second terminals of the LEDs. The first transistor switches are further connected to the drive power circuit to receive multiple drive currents, and are further connected to the gate circuit unit to receive a timing input. The at least one second transistor switch is further connected to the gate circuit unit to receive a timing input. The light emitting display device can have reduced parasitic capacitance effect, and thus reduced power consumption and have improved display quality.
    Type: Application
    Filed: June 21, 2023
    Publication date: February 29, 2024
    Applicant: MACROBLOCK, INC.
    Inventors: Li-Chang YANG, Yi-Sheng LIN
  • Publication number: 20240074175
    Abstract: A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.
    Type: Application
    Filed: February 23, 2023
    Publication date: February 29, 2024
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG
  • Patent number: 11914885
    Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang, Hun Wook Lee
  • Patent number: 11914931
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 27, 2024
    Assignee: ANSYS, INC.
    Inventors: Akhilesh Kumar, Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
  • Patent number: 11914941
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Publication number: 20240046946
    Abstract: A method includes obtaining, using at least one processing device, noisy speech signals and extracting, using the at least one processing device, acoustic features from the noisy speech signals. The method also includes receiving, using the at least one processing device, a predicted speech mask from a speech mask prediction model based on a first acoustic feature subset and receiving, using the at least one processing device, a predicted noise mask from a noise mask prediction model based on a second acoustic feature subset. The method further includes providing, using the at least one processing device, predicted speech features determined using the predicted speech mask and predicted noise features determined using the predicted noise mask to a filtering mask prediction model. In addition, the method includes generating, using the at least one processing device, a clean speech signal using a predicted filtering mask output by the filtering mask prediction model.
    Type: Application
    Filed: November 22, 2022
    Publication date: February 8, 2024
    Inventors: Chou-Chang Yang, Ching-Hua Lee, Rakshith Sharma Srinivasa, Yashas Malur Saidutta, Yilin Shen, Hongxia Jin
  • Publication number: 20240021917
    Abstract: A fire-spreading prevention battery module includes a plurality of battery cells, a plurality of fire-spreading prevention pads, an upper battery frame, a plurality of upper electrode plates, a lower battery frame, a plurality of first lower electrode plates and two second lower electrode plates. Each battery cell is formed in a cylinder shape. Each fire-spreading prevention pad wraps a peripheral surface of one battery cell. The plurality of the upper electrode plates are mounted on an upper surface of the upper battery frame. The plurality of the first lower electrode plates are mounted to a middle of a lower surface of the lower battery frame. The two second lower electrode plates are mounted to two ends of the lower surface of the lower battery frame. The plurality of the first lower electrode plates are arranged between the two second lower electrode plates.
    Type: Application
    Filed: April 16, 2023
    Publication date: January 18, 2024
    Inventors: JEN-KAI HUANG, PING-YU LEE, HSU-LUN HSU, SSU-YING CHEN, TA-CHANG YANG, MIN-YU WU, MING-CHIA CHI
  • Publication number: 20240013743
    Abstract: A cholesteric liquid crystal (ChLC) display and driving method thereof are provided. The ChLC display has a driving circuit for providing voltage on a scan line and a data line so as to drive a pixel. The driving circuit provides a first voltage and a second voltage to the data and the scan lines during a first time period, a third voltage to the data line and/or a fourth voltage to the scan line during a second time period, a fifth voltage and a sixth voltage to the data and the scan lines during a third time period. The first and sixth voltages are high levels, the second and fifth voltages are low levels, the levels of the third and fourth voltages are between the high and low levels.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 11, 2024
    Inventors: Chia-Che WU, Wu-Chang YANG, Chi-Chang LIAO
  • Patent number: 11860476
    Abstract: The invention refers to a diffusion plate and a backlight module having the diffusion plate. The diffusion plate comprises a plate-body and a plurality of pyramid-like structures arranged on a surface of the plate-body. Each pyramid-like structure has a bottom surface, a first convex portion and a second convex portion. The first convex portion and the second convex portion have different vertex angles, and therefore the pyramid-like structure can also be called as “pyramid-like structure with multiple vertex angles”. The pyramid-like structures with multiple vertex angles can increase the light splitting points, which can improve the light splitting effect of the diffusion plate. The light source of a single light-emitting diode can be divided into eight point-light sources (light splitting points) or more, which is double the number of light splitting points compared with the traditional pyramid structure with single vertex, and thus can greatly improve the light diffusion effect.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: January 2, 2024
    Assignee: Entire Technology Co., Ltd.
    Inventors: Yan-Zuo Chen, Hung Han Kao, Tsung-Chang Yang
  • Patent number: 11852941
    Abstract: A cholesteric liquid crystal display device includes a solar cell, a first substrate, a shielding layer, a first electrode layer, a cholesteric liquid crystal layer, a second electrode layer and a second substrate stacked sequentially from bottom to top. The solar cell includes a metal wiring pattern layer. The shielding layer corresponds to the upper side of the metal wiring pattern layer, and is used to reduce the reflection of light from the metal circuit pattern layer. In this way, the cholesteric liquid crystal display device replaces the traditional black absorbing layer with the black material of the solar cell, which can not only absorb light, but also display the image with self-sustaining power. The cholesteric liquid crystal display device shields the arrangement of the metal wiring pattern layer through the shielding layer, which can ensure the image quality of the display panel.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 26, 2023
    Assignee: IRIS OPTRONICS CO., LTD.
    Inventors: Wu-Chang Yang, Hung Tien Chen, Chi-Chang Liao
  • Patent number: 11856056
    Abstract: Systems, methods, and devices for decentralized notification services are disclosed. In some aspects, the techniques described herein relate to: providing a distributed notification service configured to execute on each node of a plurality of nodes of a decentralized peer-to-peer platform; determining, by the distributed notification service of a first node, a notification definition, where the notification definition is from a catalog of notification definitions and included in a distributed application executing on the first node; sending, by the distributed notification service of a second node, a notification message, where the notification message is associated with the notification definition; receiving, by the distributed notification service of the first node, the notification message; and delivering, by the distributed notification service of the first node, the notification message in the distributed application executing on the first node.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: December 26, 2023
    Assignee: JPMORGAN CHASE BANK , N.A.
    Inventors: Ramesh Babu Anandhan, Chang Yang Jiao, Sudhir Upadhyay, Thomas Eapen, Tulasi Movva, Suresh Shetty
  • Publication number: 20230386426
    Abstract: The present invention relates to a driving method of a cholesteric liquid crystal display. It includes the steps in the following: driving each scan line by a dynamic driving scheme (DDS) including an Evolution phase; refreshing a frame of the cholesteric liquid crystal display by a full refresh mode, each scan line driven N times during the Evolution phase in the full refresh mode; and refreshing a part of the frame by a partial-refresh mode, each scan line driven M times in the Evolution phase in the partial-refresh mode, wherein M is greater than N.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 30, 2023
    Inventors: MING-LIANG TSAI, WU-CHANG YANG, CHI-CHANG LIAO
  • Publication number: 20230368747
    Abstract: The present invention relates to a cholesteric liquid crystal display, a micro processing unit, and a method for hybrid driving. The cholesteric liquid crystal display comprises a display panel and a micro processing unit. First, a grayscale threshold value needs to be set in advance. The micro processing unit will change the grayscale value of the display unit exceeding the grayscale threshold value to the new grayscale value displayed by the bright state color, and display the image by the DDS driving mode. Then the micro processing unit drives the display image in the PWM drive mode, which can greatly improve the color level and contrast display effect of the image.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 16, 2023
    Inventors: SHENG-YAO WANG, WU-CHANG YANG, CHENG-HUNG YAO, CHI-CHANG LIAO
  • Patent number: 11818892
    Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: November 14, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Publication number: 20230345725
    Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 26, 2023
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Hae Chang YANG
  • Publication number: 20230344901
    Abstract: Systems, methods, and devices for decentralized notification services are disclosed. In some aspects, the techniques described herein relate to: providing a distributed notification service configured to execute on each node of a plurality of nodes of a decentralized peer-to-peer platform; determining, by the distributed notification service of a first node, a notification definition, where the notification definition is from a catalog of notification definitions and included in a distributed application executing on the first node; sending, by the distributed notification service of a second node, a notification message, where the notification message is associated with the notification definition; receiving, by the distributed notification service of the first node, the notification message; and delivering, by the distributed notification service of the first node, the notification message in the distributed application executing on the first node.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Ramesh Babu ANANDHAN, Chang Yang JIAO, Sudhir UPADHYAY, Thomas EAPEN, Tulasi MOVVA, Suresh SHETTY
  • Patent number: 11798624
    Abstract: There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a plurality of memory blocks each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit for performing a general operation including a program operation, a read operation, and an erase operation on the plurality of memory blocks; and a control logic for controlling the peripheral circuit to operate in a heating mode in which the peripheral circuit applies heat to the plurality of memory blocks.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Kyung Min Kim, Hae Chang Yang
  • Publication number: 20230325528
    Abstract: A method for privacy preserving machine learning model sharing may include a computer program for a first institution of a plurality of institutions in a distributed ledger network: receiving transaction data for a transaction; training a local machine learning model using the transaction data; submitting parameters for the local machine learning model to the distributed ledger network as a private transaction with a trusted entity, wherein the trusted entity receives parameters for a plurality of local machine learning models from the distributed ledger network for the plurality of institutions in the distributed ledger network and aggregates the parameters into an aggregated machine learning model and submits the aggregated parameters to the distributed ledger network as one or more transactions; receiving, from the distributed ledger network, the aggregated parameters for the aggregated machine learning model; and updating the local machine learning model with the aggregated parameters.
    Type: Application
    Filed: June 8, 2022
    Publication date: October 12, 2023
    Inventors: Sudhir UPADHYAY, Monik Raj BEHERA, Suresh SHETTY, Tulasi MOVVA, Palka PATEL, Vinay SOMASHEKAR, Thomas EAPEN, Chang Yang JIAO
  • Patent number: D1000848
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: October 10, 2023
    Inventor: Xing Chang Yang
  • Patent number: RE49768
    Abstract: A wind power converter device is provided. The wind power converter device includes grid side converters, generator side converters and a DC bus module. Each of the grid side converters includes grid side outputs electrically coupled to a grid and a first and a second DC inputs. Each two of the neighboring grid side converters are connected in series at the second and the first DC inputs. Each of the generator side converters includes generator side inputs electrically coupled to a generator device and a first and a second DC outputs. Each two of the neighboring generator side converters are coupled in series at the second and the first DC outputs. The DC bus module is electrically coupled between the grid side converters and the generator side converters.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 26, 2023
    Inventors: Chang-Yang Wang, Li Cai, Yan-Song Lu