Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.

Abstract: A flip chip light emitting diode includes a semiconductor layer comprising an epitaxial layer an N-semiconductor layer, a light active layer and a P-semiconductor layer arranged from top to bottom in series. A first electrode mounted on the semiconductor layer. A second electrode mounted on the semiconductor layer. A insulating layer mounted on the semiconductor layer. The N-semiconductor layer protrudes away from the epitaxial layer to form a protruding portion. The light active layer and the P-semiconductor layer mounts on the protruding portion in series. The insulating layer mounts between the first electrode and the protruding portion, the light active layer, the P-semiconductor layer and the second electrode. The flip chip light emitting diode also comprises a supporting portion, the supporting portion is mounted on a top surface of the epitaxial layer by a connecting portion. The connecting portion has same or different materials with the supporting portion.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer.

Abstract: A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

Abstract: An edge stabilizer for a composite structure includes an elongate edge support segment, defining a geometric shape of an edge of the composite structure, and a connector, configured to attach the edge support segment to the edge of the composite structure. The edge support segment comprises first and second halves configured to attach together around the edge, each half including a shoulder, opposing mating relationship of the shoulders defining a slot for receiving the edge. The edge stabilizer can be part of a system for stabilizing an edge of a composite barrel section. The system can also include a moveable cart, the barrel section being supportable upon the cart.

Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.

Abstract: A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Abstract: A network switch, a device management system, and a device management method thereof are provided. A network management system with a graphical management interface is embedded in the network switch, so that network administrators can use web browser for management. The graphical management interface provides a topology mode, a floor mode and a map mode for the network administrators to intuitively manage Internet Protocol (IP) connected apparatuses on a topological diagram, a floor plan or a map. Furthermore, in response to a control operation corresponding to the IP connected apparatus on the graphical management interface, the network switch performs a device function operation (e.g., an information collecting operation, a configuration setting operation, a node searching operation, a system login operation, etc.) corresponding to the control operation through a communication module thereof. Accordingly, an innovative and convenient device management system can be provided for the network administrators.

Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens has negative refractive force, wherein both surfaces thereof can be aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.

Abstract: Organic metal compounds, and organic light-emitting devices employing the same, are provided. The organic metal compound has a chemical structure represented by formula (I): wherein each R1 can be independently hydrogen, C1-12 alkyl group, C5-10 cycloalkyl group, C3-12 heteroaryl group, or C6-12 aryl group; R2 can be independently hydrogen, halogen, C1-12 alkyl group, C5-10 cycloalkyl group, C3-12 heteroaryl group, or C6-12 aryl group.

Abstract: A method of forming a semiconductor device includes etching an inter-layer dielectric (ILD) to form a contact opening exposing a portion of a source/drain (S/D). The method further includes depositing a titanium-containing material into the contact opening, wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of the ILD to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

Abstract: A buffer write method for a buffer, including a plurality of M-bit storage units, has following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; calculating a corresponding start address of the buffer for the pixel data of the first N-bit pixels; and storing the first N-bit pixels of the picture according to the calculated start address of the buffer in the M-bit storage units by a buffer controller. The storing step includes fully storing at least one of the first N-bit pixels in one of the M-bit storage units storage units, wherein M and N are positive integers, and M is not divisible by N.

Abstract: The present invention concerns chimeric or humanized antibodies or antigen-binding fragments thereof that comprise specific CDR sequences, disclosed herein. Preferably, the antibodies or fragments comprise specific heavy and light chain variable region sequences disclosed herein. More preferably, the antibodies or fragments also comprise specific constant region sequences, such as those associated with the nG1m1,2 or Km3 allotypes. The antibodies or fragments may bind to a human histone protein, such as H2B, H3 or H4. The antibodies or fragments are of use to treat a variety of diseases that may be associated with histones, such as autoimmune disease (e.g.

Abstract: Provided is a material composition and method for that includes providing a primer material including a surface interaction enhancement component, and a cross-linkable component. A cross-linking process is performed on the deposited primer material. The cross-linkable component self-cross-links in response to the cross-linking process to form a cross-linked primer material. The cross-lined primer material can protect an underlying layer while performing at least one process on the cross-linked primer material.

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

Abstract: A four-piece optical lens for capturing image and a five-piece optical module for capturing image are provided. In the order from an object side to an image side, the optical lens along the optical axis includes a first lens with positive refractive power; a second lens with refractive power; a third lens with refractive power; and a fourth lens with refractive power; and at least one of the image-side surface and object-side surface of each of the four lens elements are aspheric. The optical lens can increase aperture value and improve the imaging quality for use in compact cameras.