Patents by Inventor Chang AN
Chang AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10162414Abstract: A wireless control device adapted to detect a signal from a signal source for generating a corresponding first sensing signal and wirelessly transmit the first sensing signal to a host is provided. The wireless control device includes a position calibrator and an accessory. The position calibrator includes a first main body, a first coupling structure disposed on the first main body, at least one position sensing element adapted to detect the signal, a first microprocessor electrically connected to the position sensing element and a wireless transmitting module electrically connected to the first microprocessor and wirelessly transmitting the first sensing signal to the host. The accessory includes a second main body and a second coupling structure disposed on the second main body. A position calibrator and an accessory detachably assembled with the position calibrator to form a wireless control device are also provided.Type: GrantFiled: December 30, 2016Date of Patent: December 25, 2018Assignee: HTC CorporationInventors: Ying-Chieh Huang, Wen-Hsiung Shih, Hsi-Yu Tseng, Chih-Ting Chen, Chun-Wei Chang, Sung-Chi Tsai, Yen-Cheng Lin
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Patent number: 10161786Abstract: An illumination device comprises one or more emitter modules having improved thermal and electrical characteristics. According to one embodiment, each emitter module comprises a plurality of light emitting diodes (LEDs) configured for producing illumination for the illumination device, one or more photodetectors configured for detecting the illumination produced by the plurality of LEDs, a substrate upon which the plurality of LEDs and the one or more photodetectors are mounted, wherein the substrate is configured to provide a relatively high thermal impedance in the lateral direction, and a relatively low thermal impedance in the vertical direction, and a primary optics structure coupled to the substrate for encapsulating the plurality of LEDs and the one or more photodetectors within the primary optics structure.Type: GrantFiled: June 25, 2014Date of Patent: December 25, 2018Assignee: Lutron Ketra, LLCInventors: Kuo-Lih Chang, Mickey Malone, Horace C. Ho
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Patent number: 10163651Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.Type: GrantFiled: January 30, 2018Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
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Patent number: 10163842Abstract: A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.Type: GrantFiled: April 18, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Hung Kuo, Chin-Yu Ku, Yuh-Sen Chang, Hon-Lin Huang, Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii
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Patent number: 10165475Abstract: Technology for transcoding avoidance during a single radio voice call continuity (SRVCC) procedure is disclosed. In an example, a mobile switching center (MSC) can include circuitry configured to: receive from a mobility management entity (MME) in a SRVCC packet switch (PS) to circuit switched (CS) request message, selected CODEC information for a selected CODEC used for a user equipment (UE) in an internet protocol (IP) Multimedia Subsystem (IMS) over long term evolution (LTE) system; and communicate the selected CODEC information to a target MSC to enable the target MSC to identify the selected CODEC for the UE to allow the selected CODEC to be used in the CS domain.Type: GrantFiled: August 13, 2015Date of Patent: December 25, 2018Assignee: INTEL CORPORATIONInventors: Chang Hong Shan, Alexandre Stojanovski
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Patent number: 10164046Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.Type: GrantFiled: July 17, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 10164109Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.Type: GrantFiled: January 29, 2015Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang
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Patent number: 10164263Abstract: The present invention relates to a battery technology, and more particularly, to a current collector that may be widely used in secondary batteries and an electrode employing the same. The current collector includes a conductive fiber layer including a plurality of conductive fibers. Each of the conductive fibers includes a conductive core consisting of a plurality of metal filaments; and a conductive binder matrix surrounding the outer circumferential surfaces of the conductive core.Type: GrantFiled: June 24, 2014Date of Patent: December 25, 2018Assignee: JENAX INC.Inventors: Chang Hyeon Kim, Min Gyu Choi, Lee Hyun Shin
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Patent number: 10164242Abstract: Porous electrodes in which the porosity has a low tortuosity are generally provided. In some embodiments, the porous electrodes can be designed to be filled with electrolyte and used in batteries, and can include low tortuosity in the primary direction of ion transport during charge and discharge of the battery. In some embodiments, the electrodes can have a high volume fraction of electrode active material (i.e., low porosity). The attributes outlined above can allow the electrodes to be fabricated with a higher energy density, higher capacity per unit area of electrode (mAh/cm2), and greater thickness than comparable electrodes while still providing high utilization of the active material in the battery during use. Accordingly, the electrodes can be used to produce batteries with high energy densities, high power, or both compared to batteries using electrodes of conventional design with relatively highly tortuous pores.Type: GrantFiled: May 19, 2015Date of Patent: December 25, 2018Assignees: Massachusetts Institute of Technology, The Regents of the University of Michigan, The Regents of the University of CaliforniaInventors: Yet-Ming Chiang, Chang-Jun Bae, John William Halloran, Qiang Fu, Antoni P. Tomsia, Can K. Erdonmez
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Patent number: 10163640Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.Type: GrantFiled: October 31, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shuo Hsieh, Shih-Chang Tsai, Chih-Han Lin, Te-Yung Liu
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Patent number: 10163669Abstract: A method for thickness measurement includes forming an implantation region in a semiconductor substrate. A semiconductor layer is formed on the implantation region of the semiconductor substrate. Modulated free carriers are generated in the implantation region of the semiconductor substrate. A probe beam is provided on the semiconductor layer and the implantation region of the semiconductor substrate with the modulated free carriers therein. The probe beam reflected from the semiconductor layer and the implantation region is detected to determine a thickness of the semiconductor layer.Type: GrantFiled: January 29, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chieh Hung, Ming-Hua Yu, Yi-Hung Lin, Jet-Rung Chang
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Patent number: 10164098Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.Type: GrantFiled: October 3, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
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Patent number: 10165341Abstract: The invention discloses a method, in an OLT in a passive optical network, of identifying a long-shining rogue ONU, the method comprising the steps of: A. allocating a specific radio frequency signal at a different frequency to each of ONUs in the passive optical network; and B. when the long-shining rogue ONU is detected in the passive optical network: b1. broadcasting a control message to each of the ONUs; b2. receiving uplink signals in the uplink; b3. recovering the specific radio frequency signals transmitted by the normal ONUs from the uplink signals; and b4. identifying an absent specific radio frequency signal according to the recovered specific radio frequency signals, wherein the ONU corresponding to the absent specific radio frequency signal is the long-shining rogue ONU. The invention further discloses an OLT device performing the method and a method, in an ONU, of assisting the OLT in identifying a long-shining rogue ONU.Type: GrantFiled: October 31, 2014Date of Patent: December 25, 2018Assignee: Alcatel LucentInventor: Qingjiang Chang
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Patent number: 10163824Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.Type: GrantFiled: December 2, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shou-Zen Chang, Chung-Hao Tsai, Chuei-Tang Wang, Kai-Chiang Wu, Ming-Kai Liu
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Patent number: 10159949Abstract: This disclosure features methods of forming chemical compositions. The method includes (1) mixing a plurality of continuous material flows in a mixing tank to form a chemical composition, each continuous material flow including at least one component of the composition; and (2) moving a continuous flow of the chemical composition to a packaging station downstream of the mixing tank. The mixing and moving steps are performed continuously. This disclosure also features systems that can be used to perform such methods.Type: GrantFiled: February 14, 2017Date of Patent: December 25, 2018Assignee: Fujifilm Planar Solutions, LLCInventors: Shih-Pin Chou, Wen-Hung Chang, Deepak Mahulikar, Tamas Varga, Abhudaya Mishra
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Patent number: 10164984Abstract: A relay server includes a storage configured to store first access right information of a first cloud storage service to which a first user is subscribed and second access right information of a second cloud storage service to which a second user is subscribed. The relay server further includes a communication interface configured to request, from the first cloud storage service, first data that is stored in the first cloud storage service, based on the first access right information, and receive the requested first data from the first cloud storage. The relay server further includes a controller configured to control the communication interface to store the received first data in the second cloud storage service, based on the second access right information.Type: GrantFiled: July 29, 2015Date of Patent: December 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-jin Kim, Kyung-ah Chang, Jong-deok Choi
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Patent number: 10162277Abstract: An extreme ultraviolet (EUV) lithography system includes a collector designed to collect and reflect EUV radiation, a cover integrated with the collector, a first exhaust line connected to the cover and configured to receive debris vapor from the collector, a debris trapper connected to the first exhaust line and configured to trap the debris vapor, and a second exhaust line connected to the debris trapper.Type: GrantFiled: November 1, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chieh Chien, Jye-Fu Jeng, Shih-Chang Shih, Kun-Jin Wu, Guan-Heng Liu, Jen-Yang Chung, Li-Jui Chen, Po-Chung Cheng
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Patent number: 10163707Abstract: Methods for forming a group III-V device structure are provided. A method includes forming a first through via structure penetrating through group III-V compound layers over a front surface of a semiconductor substrate. The method also includes thinning the semiconductor substrate from a back surface of the semiconductor substrate. The method further includes etching the semiconductor substrate from the back surface to form a via hole substantially aligned with the first through via structure. In addition, the method includes etching the semiconductor substrate from the back surface to form a recess extending from a bottom surface of the recess towards the first through via structure. The first through via structure is exposed by the via hole and the recess. The method also includes forming a conductive layer in the via hole and the recess to form a second through via structure connected to the first through via structure.Type: GrantFiled: May 19, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hong Chang, Hsin-Chih Lin, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
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Patent number: 10165585Abstract: Communication equipment communicates in a licensed frequency band using a licensed band physical channel structure (licensed structure) and communicates in an unlicensed frequency communication band using an unlicensed band physical channel structure (unlicensed structure) where the unlicensed structure includes at least the same symbol times and subcarrier frequency divisions as in the licensed structure. The symbol times and subcarriers form a plurality of time-frequency communication resource elements. A set of symbol times and subcarrier frequency divisions form a licensed reference subset of communication resource elements that are allocated for reference signal transmission in the licensed structure. The same set of symbol times and subcarrier frequency divisions form an unlicensed reference subset of communication resource elements that are allocated for reference signal transmission in the unlicensed structure.Type: GrantFiled: May 22, 2015Date of Patent: December 25, 2018Assignee: Kyocera CorporationInventors: Amit Kalhan, Henry Chang, David Comstock
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Patent number: D836765Type: GrantFiled: March 21, 2017Date of Patent: December 25, 2018Assignee: Broan-NuTone LLCInventors: Benjamin Thorpe Puffer, Hyuk-Jae Chang, Jeremy Donald O'Halloran