Patents by Inventor Chang-Fu Lin

Chang-Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410954
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 9, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11380978
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes stacking an antenna board on a circuit board, and disposing between the antenna board and the circuit board a supporting body securing the antenna board and the circuit board. As such, during a packaging process, the distance between the antenna board and the circuit board is kept unchanged due to the supporting body, thus ensuring that the antenna board operates properly and improving the product yield.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 5, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shi-Min Zhou, Han-Hung Chen, Rung-Jeng Lin, Kuo-Hua Yu, Chang-Fu Lin
  • Publication number: 20220189900
    Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 16, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yu Kuo, Rui-Feng Tai, Yih-Jenn Jiang, Don-Son Jiang, Chang-Fu Lin
  • Publication number: 20220181225
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 9, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220148975
    Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Jhen Chen, Chih-Hsun Hsu, Yuan-Hung Hsu, Chih-Nan Lin, Chang-Fu Lin, Don-Son Jiang, Chih-Ming Huang, Yi-Hsin Chen
  • Patent number: 11289346
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Patent number: 11289794
    Abstract: An electronic package is disclosed. An antenna board is stacked on a circuit board. A frame is formed on the circuit board. A supporter disposed between the antenna board and the circuit board is secured in the frame. In a packaging process, the frame ensures that the antenna board and the circuit board are separated at a distance that complies with a requirement, and that the antenna function of the antenna board can function normally.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: March 29, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Rung-Jeng Lin, Han-Hung Chen, Shi-Min Zhou, Kuo-Hua Yu, Chang-Fu Lin
  • Publication number: 20220093518
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 24, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220068663
    Abstract: An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.
    Type: Application
    Filed: October 13, 2020
    Publication date: March 3, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chih-Ming Huang, Kuo-Hua Yu, Chang-Fu Lin
  • Patent number: 11227842
    Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 18, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chang-Fu Lin, Chun-Tang Lin, Bo-Hao Chang
  • Publication number: 20210343546
    Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.
    Type: Application
    Filed: June 8, 2020
    Publication date: November 4, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
  • Patent number: 11164755
    Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 2, 2021
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
  • Publication number: 20210320076
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, the arrangement of the bump body and the metal auxiliary layer allows complete reaction of the IMCs after reflowing the solder layer, and the volume of the conductive structures will not continue to shrink. As such, the problem of cracking of the conductive structures can be effectively averted.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 14, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20210296295
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
  • Publication number: 20210287962
    Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.
    Type: Application
    Filed: May 12, 2020
    Publication date: September 16, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Publication number: 20210280530
    Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 9, 2021
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Chih-Hsun Hsu, Chee-Key Chung, Jia-Wei Pan, Chang-Fu Lin
  • Patent number: 11101566
    Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Han-Hung Chen, Chun-Yi Huang, Chang-Fu Lin, Rung-Jeng Lin, Kuo-Hua Yu
  • Patent number: 11102890
    Abstract: This present disclosure provides an electronic package and a method for manufacturing the same. An antenna board with a limiter is stacked on a circuit board. A support body for holding the antenna board and the circuit board in place is provided between the antenna board and the circuit board, such that in the process of forming the support body, the limiter stops the flow of an adhesive material of the support body, and the adhesive material of the support body is prevented from overflowing onto an antenna structure of the antenna board to make sure that the antenna of the antenna board functions properly.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 24, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ying-Chang Tseng, Yuan-Hung Hsu, Chang-Fu Lin
  • Patent number: 11069661
    Abstract: An electronic package is formed by arranging two encapsulating portions of different materials between a plurality of electronic components stacked to each other to adjust a stress distribution of the electronic package, so that the degree of warpage of the electronic package can be optimally controlled.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 20, 2021
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wei-Jhen Chen, Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11056470
    Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 6, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu