Abstract: A method for forming an isolation layer of a semiconductor device is disclosed. The method has a wet etching separately performed two times or more without a conventional chemical mechanical polishing process. In the method, a silicon substrate in which an active region and a field region are defined is provided, and a trench is formed in the silicon substrate within the field region. An insulating layer to be used as the isolation layer is then formed on the silicon substrate including the trench. Thus the trench is filled with the insulating layer. Next, a capping layer is formed on a resultant entire structure including the insulating layer, and selectively removed to expose an upper portion of the insulating layer in the active region. The exposed insulating layer in the active region is then removed by a first wet etching, and the residual capping layer is removed by a second wet etching. Accordingly, the isolation layer is obtained from the insulating layer remaining in the trench.

Abstract: A method for forming an isolation layer of a semiconductor device is disclosed. The method has a wet etching separately performed two times or more after the chemical mechanical polishing process. In the method, a silicon substrate having an active region and a field region is provided, and a trench is formed in the silicon substrate within the field region. An insulating layer to be used as the isolation layer is then formed on the silicon substrate including the trench. Thus the trench is filled with the insulating layer. Next, a capping layer is formed on a resultant entire structure including the insulating layer, and selectively removed by the chemical mechanical polishing process to expose an upper portion of the insulating layer in the active region. A point in time when the upper portion is exposed is used as an end point of the selective removal.

Abstract: A cervical pillow for protection of cervical vertebrae includes a pillow body filled with stuffing materials, the pillow body having a neck supporting section which is formed at a front center portion of the pillow body, a concaved section which is formed behind the neck supporting section, and a pair of auxiliary supporting sections which are respectively formed at both sides of the neck supporting section and each of which is defined with an ear accommodating opening. The neck supporting section is formed to have a height which enables the cervical vertebrae to preserve their normal C-shaped lodortic curvature when the neck supporting section supports the neck of a user while the user lies down. Each auxiliary supporting section is formed to have a front height and a rear height which are greater than the height of the neck supporting section so that the cervical vertebrae and thoracic vertebrae are held parallel to a bed when the user lies on his or her side.

Abstract: Disclosed is a chemical mechanical polishing(“CMP”) apparatus. The present invention provides a CMP apparatus having a rotatable wafer holder in which a wafer is fixed. At a bottom of the wafer holder, a pair of driving roller is arranged and the respective rollers are rotated by motors. A polishing wire is winded between the respective driving rollers, the polishing wire is stuck to the wafer fixed at the wafer holder and the polishing wire moves in a linear reciprocal movement. Meanwhile, guide-rollers for providing tension with the polishing wire are arranged at outer portions of the respective driving rollers thereby winding both ends of the polishing wire at the respective guide-rollers. Further, a height adjusting member for is arranged at bottom portions of the polishing wire thereby adjusting the height of the polishing wire owing to a rise of the height adjusting member.

Abstract: A method for planarizing a semiconductor substrate uses a difference in etch selectivity of insulators on the semiconductor substrate. The method comprises the steps of wet-etching the second and first insulating layers at upper edges of the elevated region until portions of the first insulating layer are exposed at the upper edges, forming a third insulating layer on the first and second insulating layers, and wet-etching the third and second insulating layers until an upper surface of the first insulating layer is exposed. During the wet-etching, the second insulating layer is etched faster than the third insulating layer. With this method, the semiconductor substrate has an even surface.

Abstract: The present invention discloses a method of a shallow trench isolation of a semiconductor device. The method comprises the steps of: forming a mask layer having a silicon layer on a semiconductor substrate; forming a trench mask pattern by etching a selected portion of the mask layer; forming a trench by etching the semiconductor substrate by using the trench mask pattern; forming an insulating layer for filling on the trench mask pattern so as to fill the trench; forming a crack in the insulating layer for filling formed on the trench mask pattern; removing a selected portion of the insulating layer for filling; and removing the trench mask pattern.

Abstract: A method is disclosed for manufacturing a semiconductor device that is capable of minimizing a step difference between DRAM and logic regions of a semiconductor substrate by forming a capacitor in the DRAM cell region and then forming a metal interconnection in the logic region after deposition of a first insulating layer before planarization, the metal interconnection having height similar to the capacitor. Although a second insulating layer is deposited over the substrate, a step between the DRAM cell region and local region can be minimized because of the metal interconnection formed in the logic region. Thus, although only either CMP or etch back process is used, planarization of the second insulating layer is allowed.

Abstract: Methods of forming trench isolation regions include the steps of forming a trench in a semiconductor substrate having a surface thereon and then depositing an electrically insulating layer on the semiconductor substrate, to fill the trench. This depositing step is preferably performed by depositing an electrically insulating layer (e.g., SiO.sub.2) using a plasma chemical vapor. A mask layer is then formed on the electrically insulating layer. According to a preferred aspect of the present invention, the mask layer is planarized using chemical mechanical polishing, for example, to define a mask having openings therein that expose first portions of the electrically insulating layer extending opposite the surface. These first portions are also self-aligned to and extend opposite active portions of the substrate. The exposed portions of the electrically insulating layer are then etched using the mask as an etching mask.

Abstract: Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region.

Abstract: An isolation region is formed on a substrate by forming spaced apart mesas on the substrate, each mesa including a barrier region which caps the mesa. An insulation riser is then formed in the substrate, disposed between and separated from the spaced apart mesas. Spaced apart trenches are formed in the substrate on opposite sides of the insulation riser, each trench disposed between the insulation riser and a respective one of the mesas. An insulating material layer is formed on the substrate, the insulating material layer filling the spaced apart trenches and covering the insulation riser and the mesas, and then is chemical mechanical polished to expose the mesas and thereby form an isolation region spanning the spaced apart trenches. Preferably, barrier spacers are formed on sidewall portions of the mesas, and a surface portion of the substrate between the barrier regions is thermally oxidized using the barrier regions and the barrier spacers as an oxidation barrier to form the insulation riser.

Abstract: A method of forming an isolating trench device in a semiconductor device comprising the steps of; sequentially forming a first material layer and a second material layer over a surface of a semiconductor substrate, exposing a portion of the semiconductor substrate in which a device isolation region is to be formed by selectively etching the first and second material layers, forming side wall spacers on exposed lateral sidewalls of the first and second material layers, forming a trench by etching the exposed portion of the semiconductor substrate using the side wall spacers as a mask, depositing an insulating film having an underlayer dependency characteristic over the surface of the resulting structure, etching the surface of the insulating film, and removing the first and second material layers.

Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Abstract: This invention relates to a finger acupuncture needle puncturing position indicating apparatus in which a code reference book of symptoms (103) describing in detail symptoms of affected regions of a human body is attached to a side of the interior surface of a cover (503) on which human body anatomical charts (101) showing proper code numbers for each region are also mounted; underneath the book is a needle box (403) with a door (402) capable of storing a number of needles (401); displayed on a lighted display panel (102) mounted on the body (502) of a case are the palm and back of a hand indicating needle-puncturing positions; and mounted on one side of the body (502) of the case are a keyboard (201) with a number of keys for inputting code numbers from the human body anatomical charts (101) and the code reference book of symptoms (103) as well as a display button (202) for outputting these codes.

Abstract: A method for forming an inter-metal dielectrics in a semiconductor device includes the steps of sequentially forming a first and second insulating layers over a semiconductor substrate with a patterned metal layers, etching-back the second insulating layer so as to form second insulating spacers over the side walls of the first insulating layer, and growing a third insulating layer over the first and second insulating layers, the growing speed of the third insulating layer being different from the region over the first insulating layer to the region over the second insulating layer.