Abstract: Provided is an electronic apparatus and a method thereof. The method includes identifying pickup item information, identifying at least one storage place corresponding to the pickup item information among a plurality of storage places in the item storage center based on information on or regarding an item group located at each of the plurality of storage places, and providing information on the identified storage place and the pickup item information to a manager terminal, wherein the item group comprises at least one same item corresponding to an item group, and at least a portion of a plurality of item groups comprising a same item are stored in different storage places in the item storage center.

Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.

Abstract: Disclosed is a machine learning-based air handler and a control method thereof, the control method including collecting first data on an air quality of air flowing into the air handler, controlling a purification part based on the first data, collecting second data on an air quality of air passing through the purification part, and controlling the purification part according to a machine-learning model generated based on a setting value related to a control of the purification part, the first data, and the second data.

Abstract: A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

Abstract: An arithmetic circuit includes an arithmetic driving circuit and a detection circuit. The arithmetic driving circuit is configured to generate an arithmetic result value based on first and second arithmetic target values. The detection circuit is configured to detect whether an upper borrow digit value occurs, by receiving the arithmetic result value as feedback.

Abstract: A logic circuit includes a first pull-up driving circuit configured to drive a first inverted input signal to a supply voltage based on a first input signal, and configured to pull up an output signal based on the first input signal, a second input signal, and a third inverted input signal. The logic circuit also includes a first pull-down driving circuit configured to drive the third inverted input signal to a ground voltage based on the third input signal, and configured to pull down the output signal based on the first inverted input signal, the second input signal, and the third input signal.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.

Abstract: A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: The systems and methods for receiving a user input for a combination of a plurality of object pointers, wherein the object pointers are associated with a corresponding plurality of items located within a first area; retrieving one or more system parameters comprising a current location and a current container; transmitting a request for the combination of the plurality of object pointers, the request comprising the one or more system parameters; receiving the combination of the plurality of object pointers in response to the request; displaying locations of the plurality of items relative to the current location; and processing the plurality of items until a threshold capacity of the current container is reached by receiving input data corresponding to the plurality of object pointers.

Abstract: Provided is an electronic apparatus and a method thereof. The method includes identifying pickup item information, identifying at least one storage place corresponding to the pickup item information among a plurality of storage places in the item storage center based on information on or regarding an item group located at each of the plurality of storage places, and providing information on the identified storage place and the pickup item information to a manager terminal, wherein the item group comprises at least one same item corresponding to an item group, and at least a portion of a plurality of item groups comprising a same item are stored in different storage places in the item storage center.

Abstract: A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.

Abstract: A gas concentration measurement device is disclosed. The gas concentration measurement device comprises: a light source unit for emitting light into the gas concentration measurement device; an incident unit for refracting the light emitted from the light source unit; a first reflection unit and a second reflection unit for reflecting the incident light; a rotatable third reflection unit; and a light receiving unit for measuring the amount of incident light, wherein the light incident from the incident unit is reflected between the first reflection unit and the second reflection unit through the third reflection unit, and the light is incident on the light receiving unit by allowing an optical path thereof to be changed according to the rotation of the third reflection unit.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: A real-time utterance verification system according to the present invention includes a speech recognition unit configured to recognize an utterance of an utterer, a memory configured to store a program for verifying the utterance of the utterer in real time, and a processor configured to execute the program stored in the memory, wherein, upon executing the program, the processor generates and stores a list of the utterance of the utterer, performs a semantic analysis on each utterance included in the list, and generates, when the utterance is determined to be an inappropriate utterance for a listener as a result of the semantic analysis, utterance restricting information corresponding to the inappropriate utterance.

Abstract: A semiconductor device includes a buffer control circuit and an operation control circuit. The buffer control circuit generates an enable signal based on a self-refresh signal and to generate an end control signal and a supply control signal from a first internal chip selection signal during a self-refresh operation. The operation control circuit generates a frequency information signal from an internal command/address signal when an update signal is inputted during a mode register write operation, adjusts a shift amount based on the frequency information signal when the supply control signal is inputted during the mode register write operation, and generates an internal write command according to the adjusted shift amount during a read-modify-write operation in synchronization with an internal clock signal after generating an internal read command.

Abstract: A wireless power transmitting device according to an embodiment may include a power transmission circuit and a processor. The processor may be configured to control the power transmission circuit to wirelessly transmit power to a first area around the wireless power transmitting device, perform a predetermined first operation when an obstacle is detected in a second area around the first area, and perform a predetermined second operation when it is detected that the obstacle has entered the first area.