Abstract: A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: Disclosed is an optical gas sensor. The optical gas sensor includes: a light source which emits light; a gas collector which includes a cavity to be filled with gas to be sensed; an optical wave guider which guides light emitted from the light source to be output to the cavity, and guides the output light to be output again to the cavity after passing through the cavity of the gas collector; and an optical detector which detects light output from the optical wave guider. Thus, a path of light exposed to the gas to be sensed is increased within the cavity, thereby achieving miniaturization and sensing gas of low-concentration.

Abstract: A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub-matrix and a second sub-matrix. The first sub-matrix includes column vectors having an odd weight. The second sub-matrix includes an up matrix and a down matrix. Each of the up matrix and the down matrix includes column vectors having an odd weight.

Abstract: A semiconductor device may be provided. The semiconductor device may include a latch control signal generation circuit configured to compare a count signal counted according to the number of times that a command is inputted to the latch control signal generation circuit with a random signal having a random combination to generate a latch control signal which is enabled, based on an update signal. The semiconductor device may include a storage circuit configured to latch an address to generate a latched address, based on the latch control signal. The semiconductor device may include an internal circuit configured to receive the latched address to execute an internal operation.

Abstract: A semiconductor device may be provided. The semiconductor device may include an error scrub control circuit and or an active period signal generation circuit. The error scrub control circuit may be configured to generate an error scrub pre-charge signal and an error scrub bank signal for performing an error scrub operation of memory cells included in banks, based on a bank active signal and a row address signal which are generated based on a refresh signal. The active period signal generation circuit may be configured to generate an active period signal from the bank active signal and the error scrub pre-charge signal based on the error scrub bank signal.

Abstract: A synaptic transistor based on a metal nano-sheet and a method thereof are provided. A self-assembled floating gate layer is formed. The floating gate layer prevents leakage of electric charges transmitted from a channel layer, and also temporarily stores the transmitted electric charge. Thus, the synaptic transistor may be used as an effective memory for storing.

Abstract: Methods and apparatuses are provided for controlling a wireless power transmitting device. Information is received about a position of an electronic device from another wireless power transmitting device. Power is transmitted to the electronic device using the information about the position of the electronic device received from the other wireless power transmitting device.

Abstract: Disclosed are methods and apparatuses for object recognition using an artificial neural network. An object recognition apparatus includes an adjacent pixel setter configured to set the neighboring pixel pairs in the image frame, each neighboring pixel pair including first pixel and one or more second pixels adjacent to the first pixel, a labeler configured to label the first pixel using deep neural network-based model based on probability density function value of the neighboring pixel pairs, and an object recognizer configured to recognize an object based on the labeled first pixel.

Abstract: Disclosed is an apparatus and method to train an autonomous driving model. The apparatus includes a driver information collection processor configured to collect driver information while a vehicle is being driven. The apparatus also includes a sensor information collection processor configured to collect sensor information from a sensor installed in the vehicle while the vehicle is being driven, and a model training processor configured to train the autonomous driving model based on the driver information and the sensor information.

Abstract: A semiconductor device includes a command input circuit and an internal command generation circuit. The command input circuit is synchronized with a clock signal to generate an input command which is enabled if an external command is inputted to the command input circuit. The internal command generation circuit delays the input command by a predetermined period according to a latency information signal to generate an internal command, in synchronization with a first division clock signal and a second division clock signal generated by division of a frequency of the clock signal. The predetermined period is set to be equal to a sum of a first delay amount corresponding to “N” times a cycle time of the second division clock signal and a second delay amount corresponding to “M” times a cycle time of the clock signal.

Abstract: A memory device may be provided. The memory device may include an active control section configured to output a row active signal in response to a refresh signal when an active signal is activated. The memory device may include a refresh management section configured to control the refresh signal to skip a refresh operation for an unused row address in response to a refresh command signal and a refresh skip signal, and output an active row address for controlling the refresh operation. The memory device may include a memory section configured to perform a refresh operation for only an area of a cell array corresponding to a used row address in response to the row active signal and the active row address.

Abstract: A wireless power transmitting device according to an embodiment may include a power transmission circuit and a processor. The processor may be configured to control the power transmission circuit to wirelessly transmit power to a first area around the wireless power transmitting device, perform a predetermined first operation when an obstacle is detected in a second area around the first area, and perform a predetermined second operation when it is detected that the obstacle has entered the first area.

Abstract: Disclosed is a wireless power transmitter including a power transmitting circuit, a communication circuit and a control circuit configured to perform control to wirelessly transmit a first magnitude of power for operating an electronic device through the power transmitting circuit, obtain an operation performing command enabling the electronic device to perform a first operation, increase a magnitude of the power from the first magnitude to a second magnitude based on the operation performing command, and transmit, after increasing the magnitude of the power, a first communication signal enabling the first operation to be performed through the communication circuit to the electronic device.

Abstract: A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal.

Abstract: The present invention relates to a fall detection device, which includes a sensor attached to a user and sensing a motion of the fall detection device in a plurality of coordinate axial directions; an output section capable of outputting fall information of a user; and a controller determining that the user falls down when acceleration in a first axial direction among the plurality of coordinate axial directions is changed from a positive value to a negative value based on the motion sensed by the sensor, and controlling the fall information to be output.

Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.

Abstract: The objective of the present invention is to analyze a network topology in a wireless communication system. A method for operating a node performing wireless communication comprises the steps of: decoding a packet in order to acquire information on peripheral links, for transmitting the packet, from the packet that does not use the node as a source or a destination; and transmitting, to a control node for performing scheduling, a message including the information on the peripheral links. In addition, the present invention includes the above-mentioned embodiment and the other embodiments.

Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.

Abstract: Disclosed is an apparatus and method to train an autonomous driving model. The apparatus includes a driver information collection processor configured to collect driver information while a vehicle is being driven. The apparatus also includes a sensor information collection processor configured to collect sensor information from a sensor installed in the vehicle while the vehicle is being driven, and a model training processor configured to train the autonomous driving model based on the driver information and the sensor information.