Patents by Inventor Chang Ki Baek
Chang Ki Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030888Abstract: There is provided a substrate for a surface acoustic wave device, comprising a 2-dimensional (2D) crystalline hexagonal boron nitride layer, wherein a surface acoustic wave of the surface acoustic wave device is transmitted through the 2D crystalline hexagonal boron nitride layer.Type: ApplicationFiled: November 17, 2021Publication date: January 25, 2024Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Byoung Don KONG, Seok Hyun YOON, Hyeon Su CHO, Seung Ho LEE, Gyeong Min SEO, Chang Ki BAEK
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Patent number: 11868153Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.Type: GrantFiled: December 30, 2021Date of Patent: January 9, 2024Assignee: SK hynix Inc.Inventors: Min Wook Oh, Chang Ki Baek
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Patent number: 11664382Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.Type: GrantFiled: June 22, 2021Date of Patent: May 30, 2023Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Chang-Ki Baek, Gayoung Kim, Byoung-Don Kong, Hyangwoo Kim
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Publication number: 20230072253Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.Type: ApplicationFiled: December 30, 2021Publication date: March 9, 2023Applicant: SK hynix Inc.Inventors: Min Wook OH, Chang Ki BAEK
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Publication number: 20220028857Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.Type: ApplicationFiled: June 22, 2021Publication date: January 27, 2022Inventors: Chang-Ki BAEK, Gayoung KIM, Byoung-Don KONG, Hyangwoo KIM
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Patent number: 11200944Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.Type: GrantFiled: August 4, 2020Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
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Patent number: 11049533Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.Type: GrantFiled: May 14, 2020Date of Patent: June 29, 2021Assignee: SK hynix Inc.Inventors: Min Wook Oh, Myung Kyun Kwak, Min O Kim, Chang Ki Baek
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Publication number: 20210183417Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.Type: ApplicationFiled: May 14, 2020Publication date: June 17, 2021Applicant: SK hynix Inc.Inventors: Min Wook OH, Myung Kyun KWAK, Min O KIM, Chang Ki BAEK
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Publication number: 20200381038Abstract: A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.Type: ApplicationFiled: August 4, 2020Publication date: December 3, 2020Applicant: SK hynix Inc.Inventors: Joon Woo CHOI, Chang Ki BAEK
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Patent number: 10741240Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.Type: GrantFiled: August 14, 2018Date of Patent: August 11, 2020Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
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Patent number: 10379786Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.Type: GrantFiled: September 7, 2016Date of Patent: August 13, 2019Assignee: SK hynix Inc.Inventors: Mun Seon Jang, Saeng Hwan Kim, Chang Ki Baek, Jae Woong Yun
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Publication number: 20190198086Abstract: A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.Type: ApplicationFiled: August 14, 2018Publication date: June 27, 2019Applicant: SK hynix Inc.Inventors: Joon Woo CHOI, Chang Ki BAEK
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Publication number: 20190148615Abstract: The present invention relates to a vertical nanowire thermoelectric device which includes a heat emitting portion, a substrate disposed on the heat emitting portion and including doping regions having a first n-type doping region, a first p-type doping region, a second n-type doping region, and a second p-type doping region which are arranged to be spaced apart from each other, vertical nanowire arrays including a first n-type nanowire array, a first p-type nanowire array, a second n-type nanowire array, and a second p-type nanowire array which are formed on the first n-type doping region, the first p-type doping region, the second n-type doping region, and the second p-type doping region, respectively, a lower silicide layer formed in the doping regions and a connection region which connects the first p-type doping region and the second n-type doping region, an upper silicide layer formed on the vertical nanowire arrays, a first upper electrode configured to electrically connect an upper end of the first n-tType: ApplicationFiled: November 12, 2018Publication date: May 16, 2019Inventors: Chang Ki BAEK, Ki Hyun Kim, Seung Ho Lee
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Patent number: 10014073Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.Type: GrantFiled: December 7, 2016Date of Patent: July 3, 2018Assignee: SK hynix Inc.Inventors: Mun Seon Jang, Saeng Hwan Kim, In Tae Kim, Chang Ki Baek
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Patent number: 9875994Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.Type: GrantFiled: February 18, 2016Date of Patent: January 23, 2018Assignee: SK Hynix Inc.Inventors: Chang-Ki Baek, Joon-Woo Choi
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Publication number: 20170372796Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.Type: ApplicationFiled: December 7, 2016Publication date: December 28, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, In Tae KIM, Chang Ki BAEK
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Publication number: 20170337105Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.Type: ApplicationFiled: September 7, 2016Publication date: November 23, 2017Inventors: Mun Seon JANG, Saeng Hwan KIM, Chang Ki BAEK, Jae Woong YUN
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Patent number: 9792230Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.Type: GrantFiled: October 14, 2014Date of Patent: October 17, 2017Assignee: SK hynix Inc.Inventors: Joon Woo Choi, Chang Ki Baek
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Publication number: 20170084580Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.Type: ApplicationFiled: February 18, 2016Publication date: March 23, 2017Inventors: Chang-Ki BAEK, Joon-Woo CHOI
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Patent number: 9559230Abstract: Disclosed are a solar cell and a method for manufacturing the same. The solar cell comprises asymmetric nanowires each of which has an angled sidewall, and thus incident light can be concentrated at a p-n junction portion by means of a total reflection phenomenon of light caused by the difference between the refractive indices of a semiconductor layer and a transparent electrode layer, and light absorption may increase due to an increase in the light travel distance, thus improving photoelectric efficiency. Further, the method for manufacturing the solar cell involves etching a substrate and integrally forming the substrate and a p-type semiconductor layer including the asymmetric nanowires each of which has the angled sidewalls, thereby enabling reduced manufacturing costs and simple and easy manufacture of the nanowires having the angled sidewalls.Type: GrantFiled: August 17, 2012Date of Patent: January 31, 2017Assignee: POSTECH ACADEMY—INDUSTRY FOUNDATIONInventors: Chang Ki Baek, Yoon Ha Jeong, Seong Wook Choi, Tai Uk Rim, Soo Young Park, Myung Dong Ko