Abstract: The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity.

Abstract: A semiconductor memory device includes a clock input block suitable for generating first and second internal clocks in response to an external clock, a clock correction block suitable for generating a data clock by correcting a duty ratio of the first and second internal clocks in response to a signal activated in an initial operation mode of the semiconductor memory device, and a data control block suitable for controlling data in synchronization with the data clock.

Abstract: A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.

Abstract: A semiconductor device may include a first input/output unit and a second input/output unit. The first input/output unit may operate in synchronization with an internal clock signal to output a first data as a first output data in response to a control signal or to output a transfer data generated from a second data as the first output data in response to the control signal. The second input/output unit may operate in synchronization with the internal clock signal to generate the transfer data while in a test mode. The first output data may be transmitted to a first pad.

Abstract: A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.

Abstract: An electronic device includes: a substrate; a nanowire mesh formed on the substrate and including a plurality of crossing points cross-coupled with a plurality of unit nanowires; and a first electrode and a second electrode electrically connected to the nanowire mesh.

Abstract: The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they have a large exposed surface area compared to that of a conventional straight nanowire sensor in the same limited area, thereby increasing the probability of attachment of a target material to the nanowires to thereby increase the measurement sensitivity of the sensor. Thus, a change in the electrical conductivity (conductance or resistance) of the nanowires can be sensed with higher sensitivity, suggesting that the sensor has increased sensitivity.

Abstract: A semiconductor memory device includes a clock input block suitable for generating first and second internal clocks in response to an external clock, a clock correction block suitable for generating a data clock by correcting a duty ratio of the first and second internal clocks in response to a signal activated in an initial operation mode of the semiconductor memory device, and a data control block suitable for controlling data in synchronization with the data clock.

Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.

Abstract: A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included.

Abstract: A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included.

Abstract: Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.

Abstract: Disclosed are a solar cell and a method for manufacturing the same. The solar cell comprises asymmetric nanowires each of which has an angled sidewall, and thus incident light can be concentrated at a p-n junction portion by means of a total reflection phenomenon of light caused by the difference between the refractive indices of a semiconductor layer and a transparent electrode layer, and light absorption may increase due to an increase in the light travel distance, thus improving photoelectric efficiency. Further, the method for manufacturing the solar cell involves etching a substrate and integrally forming the substrate and a p-type semiconductor layer including the asymmetric nanowires each of which has the angled sidewalls, thereby enabling reduced manufacturing costs and simple and easy manufacture of the nanowires having the angled sidewalls.

Abstract: Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.

Abstract: An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.

Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.

Abstract: An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals.

Abstract: An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a data latch unit for latching buffered data signals in synchronization with the internal clock signal, wherein the buffered data signals are produced by buffering the data signals, a flag signal generating unit for generating flag signals from the latched data signals latched in the data latch unit in response to the test signals, and a counter for producing the counting signals in response to the flag signals.