Abstract: A method of removing a photoresist may include permeating supercritical carbon dioxide into the photoresist on a substrate having a conductive structure including a metal. The photoresist permeating the supercritical carbon dioxide may be easily removable. The photoresist permeating the supercritical carbon dioxide may be removed using a photoresist cleaning solution from the substrate. The photoresist cleaning solution may include an alkanolamine solution of about 8 percent by weight to about 20 percent by weight, a polar organic solution of about 25 percent by weight to about 40 percent by weight, a reducing agent of about 0.5 percent by weight to about 3 percent by weight with the remainder being water. The photoresist may be easily removed without damaging the conductive structure in a plasma process.

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.

Abstract: A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.

Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used to clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.

Abstract: In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.

Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

Abstract: A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask.

Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

Abstract: Methods of fabricating phase change memory elements include forming an insulating layer on a semiconductor substrate, forming a through hole penetrating the insulating layer, forming a lower electrode in the through hole and forming a recess having a sidewall comprising a portion of the insulating layer by selectively etching a surface of the lower electrode relative to the insulating layer. A phase change memory layer is formed on the lower electrode. The phase change memory layer has a portion confined by the recess and surrounded by the insulating layer. An upper electrode is formed on the phase change memory layer. Phase change memory elements are also provided.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.

Abstract: A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (W?O?).

Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

Abstract: A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.

Abstract: In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor.

Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.