Patents by Inventor Chang-Ki Hong

Chang-Ki Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535052
    Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jun-yong Kim
  • Publication number: 20090121296
    Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 14, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
  • Patent number: 7531456
    Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Se-Rah Yun, Chang-Ki Hong, Bo-Un Yoon, Jae-Kwang Choi, Joon-Sang Park
  • Patent number: 7531491
    Abstract: Aqueous cleaning solutions are provided for cleaning an integrated circuit device formed on a wafer, as well as methods of cleaning a wafer using the aqueous cleaning solution. In one aspect, an aqueous cleaning solution includes a low foam surfactant, a metal corrosion inhibitor, an acidic pH control agent or an alkali pH control agent, and water.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Min, Sang-Jun Choi, Chang-Ki Hong
  • Patent number: 7524757
    Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Chang-ki Hong, Bo-un Yoon, Jae-kwang Choi
  • Publication number: 20090098804
    Abstract: A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Inventors: Jong-Heun Lim, Sung-Ho Shin, Bo-Un Yoon, Chang-Ki Hong
  • Publication number: 20090068839
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
    Type: Application
    Filed: June 19, 2008
    Publication date: March 12, 2009
    Inventors: Sung-Jun Kim, Jeong-Heon Park, Chang-Ki Hong, Jae-Dong Lee
  • Patent number: 7498263
    Abstract: A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-rah Yun, Chang-ki Hong, Jae-dong Lee
  • Patent number: 7498217
    Abstract: In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Oh, Jeong-Nam Han, Chang-Ki Hong, Kun-Tack Lee, Dae-Hyuk Kang, Woo-Gwan Shim, Jong-Won Lee
  • Publication number: 20090025755
    Abstract: Example embodiments relate to a method of treating a substrate after performing a cleaning step with a liquid chemical in a single substrate spin cleaner. A method of treating a substrate according to example embodiments may include forming a film of deionized water on a surface of the substrate during rinsing, and drying the substrate by supplying a drying gas to the water film on the surface of the substrate. When rinsing the substrate, the rotating speed of the substrate may be reduced to about 50 rpm or less to form a film of water on the surface of the substrate. The film of water may shield the surface of the substrate from direct exposure to atmospheric air. The film of water may be maintained on the surface of the substrate when commencing the supply of the drying gas. Consequently, the number of water marks on the dried substrate may be reduced or prevented.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 29, 2009
    Inventors: Dae-Hong Eom, Chang-Ki Hong, Woo-Gwan Shim, Young-Ok Kim
  • Publication number: 20090023265
    Abstract: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R1—OSO3?HA+, R1—CO2?HA+,R1—PO42—(HA+)2,(R1)2—PO4—HA+, or R1—SO3—HA+ where R1 is a straight or branched hydrocarbon group of C4 to C22 and A is ammonia or amine. The etching solution provides a high etching selectivity ratio of an oxide film to a nitride film or a polysilicon film. Therefore, in a semiconductor device fabrication process such as a STI device isolation process or a capacitor formation process, when an oxide film is exposed together with a nitride film or a polysilicon film, the etching solution can be efficiently used in selectively removing only the oxide film.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 22, 2009
    Inventors: CHANG-SUP MUN, Hyung-Ho Ko, Woo-Gwan Shim, Chang-Ki Hong, Sang-Jun Choi
  • Publication number: 20090011599
    Abstract: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Jae-Dong Lee
  • Publication number: 20090001051
    Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Publication number: 20080314868
    Abstract: The present invention provides etchant solutions including deionized water and an organic acid having a carboxyl radical and a hydroxyl radical. Methods of forming magnetic memory devices are also disclosed.
    Type: Application
    Filed: August 28, 2008
    Publication date: December 25, 2008
    Inventors: Yu-Kyung Kim, Chang-Ki Hong, Sang-Jun Choi, Jeong-Nam Han
  • Patent number: 7459370
    Abstract: In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: December 2, 2008
    Assignee: Samsung Electronics Co., ltd.
    Inventors: Dae-hyuk Kang, Jung-min Oh, Chang-ki Hong, Sang-jun Choi, Woo-gwan Shim
  • Publication number: 20080277767
    Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 13, 2008
    Inventors: Jae-Dong Lee, Yong-Pil Han, Chang-Ki Hong
  • Patent number: 7449417
    Abstract: There are provided a cleaning solution for a silicon surface containing a buffer solution including acetic acid (CH3COOH) and ammonium acetate (CH3COONH4), iodine oxidizer, hydrofluoric acid (HF), and water. In a method for fabricating a semiconductor device, a silicon substrate may have an exposed silicon surface, which may be cleaned using a cleaning solution that contains a buffer solution including acetic acid and ammonium acetate, iodine oxidizer, hydrofluoric acid, and water.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Kim, Chang-Ki Hong, Woo-Gwan Shim
  • Patent number: 7442646
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Jun Kim, Jeong-Heon Park, Chang-Ki Hong, Jae-Dong Lee
  • Patent number: 7435301
    Abstract: Disclosed are a cleaning solution for preventing damage of a silicon germanium layer when cleaning a semiconductor device including the silicon germanium layer and a cleaning method using the same. The cleaning solution of a silicon germanium layer includes from about 0.01 to about 2.5 percent by weight of a non-ionic surfactant with respect to 100 percent by weight of the cleaning solution, about 0.05 to about 5.0 percent by weight of an alkaline compound with respect to the cleaning solution and a remaining amount of pure water. The damage to an exposed silicon germanium layer can be prevented when cleaning a silicon substrate having a silicon germanium layer. Impurities present on the surface portion of the silicon germanium layer can be effectively removed.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Mun, Doo-Won Kwon, Hyung-Ho Ko, Chang-Ki Hong, Sang-Jun Choi
  • Patent number: 7435644
    Abstract: Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge insulating layer are etched to define an electrode region. The mold oxide layer is removed using an etching gas having an etch selectivity of 500 or greater for the mold oxide layer with respect to the bridge insulating layer.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Gwan Shim, Jung-Min Oh, Chang-Ki Hong, Sang-Jun Choi, Sang-Yong Kim