Abstract: In one embodiment, a semiconductor device comprises a base and a tapered wall formed on the base. The wall has a midline and also has an inner sidewall and an outer sidewall. The inner sidewall and the outer sidewall are substantially symmetrical with each other in relation to the midline. Thus, the reliability of the semiconductor capacitor structure can be improved and the throughput can be increased. Also, further scaling down of semiconductor devices can be facilitated with the principles of the present invention.

Abstract: A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask.

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.

Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Abstract: Aqueous cleaning solutions are provided for cleaning an integrated circuit device formed on a wafer, as well as methods of cleaning a wafer using the aqueous cleaning solution. In one aspect, an aqueous cleaning solution includes a low foam surfactant, a metal corrosion inhibitor, an acidic pH control agent or an alkali pH control agent, and water.

Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.

Abstract: A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.

Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.

Abstract: A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.

Abstract: In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

Abstract: Example embodiments relate to a method of treating a substrate after performing a cleaning step with a liquid chemical in a single substrate spin cleaner. A method of treating a substrate according to example embodiments may include forming a film of deionized water on a surface of the substrate during rinsing, and drying the substrate by supplying a drying gas to the water film on the surface of the substrate. When rinsing the substrate, the rotating speed of the substrate may be reduced to about 50 rpm or less to form a film of water on the surface of the substrate. The film of water may shield the surface of the substrate from direct exposure to atmospheric air. The film of water may be maintained on the surface of the substrate when commencing the supply of the drying gas. Consequently, the number of water marks on the dried substrate may be reduced or prevented.

Abstract: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R1—OSO3?HA+, R1—CO2?HA+,R1—PO42—(HA+)2,(R1)2—PO4—HA+, or R1—SO3—HA+ where R1 is a straight or branched hydrocarbon group of C4 to C22 and A is ammonia or amine. The etching solution provides a high etching selectivity ratio of an oxide film to a nitride film or a polysilicon film. Therefore, in a semiconductor device fabrication process such as a STI device isolation process or a capacitor formation process, when an oxide film is exposed together with a nitride film or a polysilicon film, the etching solution can be efficiently used in selectively removing only the oxide film.

Abstract: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.

Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.

Abstract: The present invention provides etchant solutions including deionized water and an organic acid having a carboxyl radical and a hydroxyl radical. Methods of forming magnetic memory devices are also disclosed.

Abstract: In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate.

Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.

Abstract: There are provided a cleaning solution for a silicon surface containing a buffer solution including acetic acid (CH3COOH) and ammonium acetate (CH3COONH4), iodine oxidizer, hydrofluoric acid (HF), and water. In a method for fabricating a semiconductor device, a silicon substrate may have an exposed silicon surface, which may be cleaned using a cleaning solution that contains a buffer solution including acetic acid and ammonium acetate, iodine oxidizer, hydrofluoric acid, and water.

Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.