Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal SiO.sub.2 which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: A N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal SiO.sub.2 which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: An electrically programmable read only memory or EPROM is formed by an MNOS process compatible with N-channel silicon gate manufacturing methods. Row address lines and gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions formed beneath thin field oxide. Each storage cell is an MNOS transistor having an enhancement mode MOS transistor in series with it. The gates of the MNOS transistors are program address lines for programming and are formed by first level polycrystalline silicon. Each MNOS transistor in the array is programmed to be a logic "1" or "0" by proper voltages applied to row, output and program address lines to store charge at the oxide-nitride interface and thus change the threshold voltage for selected transistors. Then readout is provided using the MOS series transistors for access. A very dense array results.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurrance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. The ROM is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned. Address lines and gates are polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.

Abstract: A static push-pull driver circuit employs an enhancement mode transistor and a low threshold "natural" transistor as its push-pull output, and two parallel gating transistors in the driver circuit for the low-threshold transistor. One of the gating transistors is also a low-threshold natural transistor, and the other is a much smaller depletion mode transistor. The depletion transistor may be formed in the channel area of the other gating transistor by an ion implant. The common gate of the two gating transistors is connected to a chip select signal.

Abstract: Closely-spaced conductors can be used in a semiconductor integrated circuit such as an MOS read only memory or ROM formed by a process compatible with standard N-channel silicon gate manufacturing methods. Address lines and gates are polysilicon strips, and output and ground lines are defined by elongated N+ regions. To allow the spacing between adjacent polysilicon address lines to be closer, alternate rows employ first or second level polysilicon which can even overlap if necessary. Each potential MOS transistor in the array is programmed to be a logic "1" or "0", such as by ion implanting through the polysilicon gates and thin gate oxide.

Abstract: A metal-gate MOS read only memory or ROM array is formed by a process compatible with N-channel silicon gate manufacturing methods for circuits peripheral to the array on the same chip. The ROM is programmed at the time the metal level of contacts and interconnections, is patterned. Address lines and gates are metal in the array, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by patterning the metal to cover the gate or not. After metal patterning, the array is ion implanted through exposed gate oxide in the gates not covered by metal so that degradation is prevented.

Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: A dynamic read/write memory cell of the one transistor N-channel silicon gate type is made by a triple-level polysilicon process which allows the bit lines to be formed by metal strips which have low resistance and which can cover the storage capacitors for alpha particle protection. Metal-to-silicon contacts are made through an intervening polysilicon segment which allows the underlying N+ silicon region to be much smaller than in prior cells. The polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: Semiconductor read only memory (ROM) or electrically programmable memory (EPROM) devices are constructed using a metal-to-silicon contact arrangement which provides small cell size. An intervening polysilicon segment allows the silicon region underlying a metal contact area to be much smaller than in prior cells. The layout and cell structure provides a high density array. The use of the polysilicon segment also prevents the occurance of problems with spiking of metal through shallow implanted N+ regions.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.

Abstract: An electrically programmable read only memory or EPROM is formed by an MNOS process compatible with N-channel silicon gate manufacturing methods. Row address lines and gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions formed beneath thin field oxide. Each storage cell is an MNOS transistor having an enhancement mode MOS transistor in series with it. The gates of the MNOS transistors are program address lines for programming and are formed by first level polycrystalline silicon. Each MNOS transistor in the array is programmed to be a logic "1" or "0" by proper voltages applied to row, output and program address lines to store charge at the oxide-nitride interface and thus change the threshold voltage for selected transistors. Then readout is provided using the MOS series transistors for access. A very dense array results.

Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate manufacturing methods. The ROM is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned. Address lines and gates are polysilicon, and output and ground lines are defined by elongated N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.