Abstract: An electrically programmable memory array of the floating gate type is made by a process which allows the edges of the floating gates to be aligned with the edges of the control gates which also form address lines. Contacts to individual cells are not needed. These factors provide a very small cell size. The source and drain regions are formed prior to applying the first level polysilicon then covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas.

Abstract: An N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal silicon oxide which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard N-channel silicon gate ROM manufacturing methods. Instead of moat programming or contact programming as is used in almost all standard processes, however, the ROM is programmed by implant after the polysilicon level of gates and interconnection has been deposited and patterned and prior to metal deposition. Address lines and gates are polysilicon, ground lines are defined by elongated N+ regions, and output lines are metal strips contacting the N+ diffused drains. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned photoresist as a mask prior to application of the polycrystalline silicon.

Abstract: A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A plurality of dummy cells are connected to each column line half instead of a single dummy cell, and one of the dummy cells is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by spacing the dummy cells along each column line half, and addressing a dummy cell which is spaced about the same distance from the sense amplifier as the selected memory cell on the other side.

Abstract: A VMOS read only memory or ROM array is formed by a process compatible with standard N-channel silicon gate manufacturing methods used for circuitry peripheral to the array. The ROM array is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned for the periphery. Each cell is formed with a very short channel in a V-shaped anisotropically etched groove. Address lines and gates are polysilicon, and the output lines are defined by elongated N+ regions. The ground or Vss connection to the source of each transistor in the array is provided by a buried N+ epitaxial layer. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.

Abstract: A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. A dummy cell is connected to each column line half and is addressed when a memory cell on the opposite side of the sense amplifier is addressed by one of the row lines. Time delay is made more equal by placing the dummy cells at about the center of each column line half. The signals on the column line halves from the dummy cell and from the selected memory cell will reach the sense amplifier at about the same time, on average.

Abstract: Circuit means for eliminating the effect of excessive threshold voltages in insulated gate field effect transistor inverter-type circuits utilizes capacitor pull-up. Capacitors are selectively coupled from various phased voltage outputs of a multi-phase voltage supply to the driver-gate of various field effect transistors to provide increased voltage during voltage pulses of the phase involved. A voltage between the threshold voltage and a required minimum noise margin is thereby added to the driver-gate input signal to overcome the threshold voltage effect. This circuit means is particularly useful in dynamic circuits such as multiphase shift registers and bipolar-to-high voltage field effect transistor coupled circuits.

Abstract: The disclosure relates to a high density, high speed random access memory (RAM) which uses one transistor per storage cell. The cells are in a matrix of rows and columns, and a sense and refresh amplifier is located in the center of each column. Row address circuitry selects one row to be read out. The data stored in the cells in the selected row are transferred to the sense and refresh amplifiers, and column address circuitry selects one of the rows to be coupled to circuitry which performs both input and output functions.