Patents by Inventor Chang-Lin (Peter) Hsieh
Chang-Lin (Peter) Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12369022Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, a network assistant information (NAI) message identifying a set of characteristics of a network connection. The UE may communicate with the network node using a communication configuration associated with the set of characteristics of the network connection. Numerous other aspects are described.Type: GrantFiled: August 4, 2022Date of Patent: July 22, 2025Assignee: QUALCOMM IncorporatedInventors: Kai-Chun Cheng, Jen-Chun Chang, Kuhn-Chang Lin, Wen-Hsin Hsia, Chia-Jou Lu, Sheng-Chih Wang, Chenghsin Lin, Yu-Chieh Huang, Chun-Hsiang Chiu, ChihHung Hsieh, Chung Wei Lin, Leong Yeong Choo
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Publication number: 20250234582Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.Type: ApplicationFiled: March 31, 2025Publication date: July 17, 2025Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250231230Abstract: The disclosure describes a method, a device, and a system for processing transmission line pulse data. In the method, the component characteristic of a protection component is determined. A voltage-current characteristic generated by applying transmission pulses to the protection component is analyzed based on the transmission line pulse data of the protection component. Based on the design window such as an operation voltage value, a breakdown voltage value, and a required current capability, a corresponding visual graph is generated to determine the characteristic, advantages, and disadvantages of the protection component more accurately.Type: ApplicationFiled: March 5, 2024Publication date: July 17, 2025Applicant: AIP Technology CorporationInventors: Tung-Yang CHEN, Pi-Yuan HSIAO, Yu-An CHEN, Chang-Lin WU
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Patent number: 12363980Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.Type: GrantFiled: February 28, 2022Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Han Wang, Ding-Kang Shih, Chun-Hsiung Lin, Teng-Chun Tsai, Zhi-Chang Lin, Akira Mineji, Yao-Sheng Huang
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Patent number: 12364008Abstract: A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.Type: GrantFiled: September 6, 2022Date of Patent: July 15, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ming-Hung Chen, Yung I Yeh, Chang-Lin Yeh, Sheng-Yu Chen
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Publication number: 20250227325Abstract: A server comprising a circuitry, wherein the circuitry is configured to perform: generating an emulator in response to a request from a first user terminal of a first user; launching an application via the emulator; receiving streaming data and interaction data via the application; rendering the streaming data with the interaction data; recording the rendered streaming data and interaction data as a clip; and storing the clip for access from the first user terminal of the first user. According to the present disclosure, the clips may be generated in a more efficient and accurate manner, and a more immersive experience on watching the clips may be provided. Moreover, the review and share of clips may be more flexible. Therefore, the user experience may be improved.Type: ApplicationFiled: January 6, 2025Publication date: July 10, 2025Inventors: Kun-Ze LI, Che-Wei LIU, You-Chang LIN, Chieh-Min CHEN, Hao-Chia CHUNG, Yu-Cheng FAN, Chia-Yi YEH, Yu-Chuan CHANG, Chi-Hao HSIEH, Yung-Chi HSU, Po-Kao TSENG, Chien-Ming LAI, Shih-Wei CHOU
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Publication number: 20250226621Abstract: A plug electrical connector and an electrical connector combination having the same are disclosed. The plug electrical connector includes a plug insulation structure; a plurality of plug terminals joined to the plug insulation structure; a movable member movably disposed on the plug insulation structure; at least one contact terminal joined to the movable member; wherein the at least one contact terminal and the movable member move simultaneously between a contact position and a retreat position. The electrical connector combination includes the aforementioned plug electrical connector and a receptacle electrical connector. The receptacle electrical connector includes a receptacle insulation structure; a plurality of receptacle terminals joined to the receptacle insulation structure; at least one detecting terminal joined to the receptacle insulation structure. The contact terminal is selectively to contact the detecting terminal, whereby certain specific functions of an electronic device are activated.Type: ApplicationFiled: December 16, 2024Publication date: July 10, 2025Inventors: MING LUO, YUNG- CHANG LIN, YU-HUNG LIN, HUNG-TIEN CHANG, HSUAN HO CHUNG
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Patent number: 12352781Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.Type: GrantFiled: March 30, 2023Date of Patent: July 8, 2025Assignee: MEDIATEK INC.Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Sheng-Wei Lei, Chang-Lin Wei, Che-Hsien Huang, Shih-Chia Chiu, Yi-Chieh Lin, Wun-Jian Lin
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Patent number: 12347690Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.Type: GrantFiled: May 23, 2024Date of Patent: July 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
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Patent number: 12342587Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.Type: GrantFiled: March 11, 2022Date of Patent: June 24, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12342616Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: March 22, 2024Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chih-Hao Wang, Chien Ning Yao, Kuo-Cheng Chiang
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Publication number: 20250203939Abstract: A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.Type: ApplicationFiled: March 26, 2024Publication date: June 19, 2025Inventors: Che Chi Shih, Chia-Hao Yu, Zhi-Chang Lin, Ku-Feng Yang, Tsung-Kai Chiu, Szuya Liao
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Patent number: 12336226Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.Type: GrantFiled: March 3, 2022Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Tsung-Han Chuang, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12336240Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.Type: GrantFiled: December 30, 2021Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12334412Abstract: An electronic package is provided in the present disclosure. The electronic package comprises: an electronic component; a thermal conductive element above the electronic component, wherein thermal conductive element includes a first metal; an adhesive layer between the electronic component and the thermal conductive element, wherein the first adhesive layer includes a second metal; and an intermetallic compound (IMC) between the first metal and the second metal.Type: GrantFiled: January 5, 2022Date of Patent: June 17, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Chang-Lin Yeh
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Publication number: 20250186385Abstract: Ophthalmic compositions including compatible solute components and/or polyanionic components are useful in treating eyes, for example, to relieve dry eye syndrome, to protect the eyes against hypertonic insult and/or the adverse effects of cationic species on the ocular surfaces of eyes and/or to facilitate recovery from eye surgery.Type: ApplicationFiled: March 3, 2025Publication date: June 12, 2025Inventors: Joseph G. Vehige, Peter A. Simmons, Joan-En Chang-Lin
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Publication number: 20250194237Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.Type: ApplicationFiled: February 25, 2025Publication date: June 12, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Huan-Chieh Su, Mao-Lin Huang, Zhi-Chang Lin
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Publication number: 20250194431Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.Type: ApplicationFiled: February 20, 2025Publication date: June 12, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
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Patent number: 12326328Abstract: There is provided an imaging system including a camera and a control host. The camera identifies ambient light intensity and performs trigger event detection in a low power mode. When the camera detects a trigger event in the low power mode, the control host is woken up. The camera also determines an exposure mode according the ambient light intensity and informs the exposure mode to the control host such that an operating mode of the control host after being woken up matches the exposure mode of the camera.Type: GrantFiled: November 29, 2022Date of Patent: June 10, 2025Assignee: PIXART IMAGING INC.Inventors: Wen-Han Yao, Wen-Cheng Yen, Han-Chang Lin
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Publication number: 20250174580Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: ApplicationFiled: January 17, 2025Publication date: May 29, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan