Abstract: A method of forming and exposing a layer of resist which will minimize or eliminate side lobe effect resulting from the use of phase shifting masks or attenuating phase shifting masks in the exposed and developed layer of resist. The curve of reflectivity as a function of resist thickness, or swing curve, is calculated using the index of refraction, n, and the extinction coefficient, k, of the resist material and plotted. An optimum thickness of the resist corresponding to a relative maximum of the swing curve is chosen. The angular velocity used to spin the resist onto wafers is selected to produce the optimum thickness. Wafers having a resist layer with the optimum thickness are then prepared, exposed, and developed. The layer of resist may have a layer of anti-reflective material on the top surface of the layer of resist if desired.

Abstract: A method is disclosed for patterning dual damascene interconnections in semiconductor chips through the use of a developer soluble ARC interstitial layer. This is accomplished by providing a silicon substrate having a composite layer of insulation deposited thereon whereby said composite layer comprises a first layer of dielectric separated from a second layer of dielectric by an intervening intermediate layer of silicon nitride. Then, two layers of photoresist are deposited with an intervening interstitial layer of water soluble anti-reflective coating (ARC). The ARC, having a relatively high refractive index, serves as a barrier to light so that the top layer of photoresist is first line patterned without affecting the second layer. The second layer of photoresist is next hole patterned. The hole pattern is transferred into the top dielectric layer and the intervening silicon nitride layer by etching.

Abstract: A method is disclosed for forming dual damascene interconnections in semiconductor chips through the use of opposite type two-layered photoresist process. A silicon substrate is provided having a composite layer comprising a first layer of dielectric separated from a second layer of dielectric by an intervening intermediate layer of silicon nitride. Then, a layer of positive (P-type) chemical amplification resist (CAR) is deposited over the composite dielectric layer. The P-type resist is next line patterned by exposing and developing it through a dark field mask. This is followed by cross-linking the remaining P-type resist by performing a hard-bake. An opposite polarity, namely, a negative (N-type) CAR is next formed over the opposite P-type resist, and hole patterned through a clear field mask. Because of cross-linking, the P-type resist is not affected during hole patterning of the opposite N-type resist.

Abstract: A simplified method is disclosed for forming dual damascene patterns using a single photoresist process. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a "clear-field" mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. The vertical hole is transferred into the middle layer of the underlying composite layer by dry etching.

Abstract: A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, via use of a two layer planarization composite, consisting of an underlying, anti-reflective coating, which enhances the flow of an overlying photoresist layer. A two phase, RIE procedure is then employed, with the initial phase exposing thick insulator in narrow shallow trench regions, but leaving the two layer planarization composite protecting the thinner insulator in the wide shallow trenches. The second phase of the RIE procedure removes thick insulator, overlying the narrow shallow trenches, resulting in a planarized topography.

Abstract: A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, by creating photoresist plugs, only in the depressed topography regions. This is accomplished using a negative photoresist layer, a de-focus exposure, and the identical mask used to create the shallow trench pattern in a positive photoresist layer. A RIE procedure, with a 1:1 etch selectivity, is used to complete the planarization process.

Abstract: Masks and methods of forming the masks for avoiding phase conflict problems in phase shifting masks used to form a number of parallel line and space patterns on a semiconductor wafer using positive photoresist. The mask uses phase shifting material between alternating pairs of parallel opaque lines. Opaque fine tips formed as extensions to the opaque parallel lines on the mask prevent phase conflict from causing bridging at the ends of the lines. The methods of forming the masks use part of the transparent substrate or an added layer as the phase shifting material.

Abstract: An improved method for fabricating self-aligned contacts in a planar insulating layer to the source/drain contact areas on field effect transistors (FETs), formed in part from a first polycide layer, is achieved using an undoped polysilicon layer as an etch-stop layer. The planar insulating layer provides a good surface for patterning a second polycide layer without intralevel shorts that would otherwise occur over a rough topography. This is of particular use for forming the array of bit lines over the array of word lines for DRAM circuits. The method involves providing a patterned undoped polysilicon layer on the gate electrodes. A planarized insulating layer, such as reflowed borophosphosilicate glass (BPSG) is then deposited and reflowed to fill the high aspect ratio recesses between the closely spaced word lines.

Abstract: A method for fabricating MOSFET devices, with narrow gate structures, and narrow spaces between gate structures, has been developed. The addition of a rough surfaced silicon layer, as part of the gate structure, minimizes the amount of reflective and scattered light, resulting during the gate photolithographic processing. The reduction in reflective and scattered greatly enhances the ability to achieve sub-micron lines and spaces. The rough surfaced silicon can remain as a part of the gate structure, and is obtained by chemical vapor deposition of either an amorphous silicon, or a hemi-spherical grained silicon film.