Abstract: An auxiliary operation device for a droplet dispenser includes a droplet sensor, an imaging device and a processor. The droplet sensor has a detected area located between a droplet dispenser and a target area, wherein the droplet sensor detects a droplet output from the droplet dispenser, and outputs a corresponding droplet detection signal. The imaging device captures an image of the target area. The processor obtains a dripping time point at which the droplet passes through the detected area according to the droplet detection signal, and determines whether the target area is shielded within a first time range according to the image, so as to evaluate whether the droplet has successfully dropped into the target area. The above-mentioned auxiliary operating device of the droplet dispenser can objectively determine whether the droplets successfully drops into the target area, and improve the accuracy of judgment.

Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.

Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.

Abstract: A lipid delivery system, a virus-like structure (VLS) vaccine constructed therefrom, and a lipid particle capable of encapsulating an mRNA molecule encoding a SARS-CoV-2-specific antigen are provided. After the lipid particle encapsulates an mRNA molecule encoding a SARS-CoV-2 antigen, a SARS-CoV-2 S1 antigen protein can be embedded on a surface of an envelope structure of the lipid under specific buffer conditions to produce a VLS vaccine with an antigen-encoding mRNA molecule encapsulated inside and an outer membrane presenting a required viral antigen protein. The vaccine has a superior specific antibody-inducing ability to a SARS-CoV-2 mRNA vaccine and a polypeptide vaccine, can maintain a long-lasting high antibody level, and can also exhibit excellent immune binding abilities for the emerging different variants.

Abstract: The present invention relates to a secondary battery in which a first region and a second region of an insulation sheet are made of different materials, and thus thermal conduction between an electrode assembly and a cap plate can be blocked, light reflection that may occur during welding can be prevented, and static electricity and alignment can be maintained.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a lower electrode disposed on a substrate; a first lower interfacial film disposed on the lower electrode; a dielectric film disposed on the first lower interfacial film; a first upper interfacial film disposed on the dielectric film; and an upper electrode disposed on the first upper interfacial film, wherein each of the first lower interfacial film and the first upper interfacial film is a conductive single film, and the first lower interfacial film and the first upper interfacial film include the same metal element, wherein electronegativity of the metal element included in each of the first lower interfacial film and the first upper interfacial film is greater than electronegativity of a metal element included in the dielectric film.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.