Patents by Inventor Chang Seo Park

Chang Seo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936052
    Abstract: Provided is a fluorine-doped tin oxide support, a platinum catalyst for a fuel cell having the same, and a method for producing the same. Also described is a high electrical conductivity and electrochemical durability by doping fluorine to the tin oxide-based support through an electrospinning process. Thus, while resolving a degradation issue of the carbon support in the conventional commercially available platinum/carbon (Pt/C) catalyst, what is designed is to minimize an electrochemical elution of dopant or tin, which is a limitation of the tin oxide support itself and has excellent performance as a catalyst for a fuel cell.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 19, 2024
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jin Young Kim, Jong Min Kim, Hee-Young Park, So Young Lee, Hyun Seo Park, Sung Jong Yoo, Jong Hyun Jang, Hyoung-Juhn Kim, Chang Won Yoon, Jonghee Han
  • Patent number: 11923610
    Abstract: In various embodiments, an antenna array may comprise a dielectric; a first patch antenna disposed on a first region of the dielectric; a second patch antenna disposed on a second region of the dielectric; and a ground layer including a first sub-ground layer in contact with a lower portion of the first region of the dielectric, a third sub-ground layer in contact with a lower portion of the second region of the dielectric, and a second sub-ground layer spaced apart from a lower portion between the first region and the second region of the dielectric.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 5, 2024
    Assignees: Samsung Electronics Co., Ltd., HONGIK UNIVERSITY INDUSTRY-ACADEMIA COOPERATION FOUNDATION
    Inventors: Jae-Hyun Park, Jeong-Hae Lee, Min-Seo Park, Young-Ho Ryu, Sung-Bum Park, Kwi-Seob Um, Chong-Min Lee, Chang-Hyun Lee
  • Publication number: 20240074258
    Abstract: An electronic device includes a display device, which may be fabricated using a described method. The display device includes a glass substrate including a first surface, a second surface opposite the first surface, and a side surface between the first surface and the second surface, an outermost structure on the first surface of the glass substrate and located adjacent to an edge of one side of the glass substrate, and a display area including a plurality of light emitting areas on the first surface of the glass substrate and located farther from the edge of the one side of the glass substrate than the outermost structure is. A minimum distance from the side surface of the glass substrate to the outermost structure is equal to 130 ?m or less.
    Type: Application
    Filed: May 5, 2023
    Publication date: February 29, 2024
    Inventors: Wan Jung KIM, Dong Jo KIM, Sun Hwa KIM, Young Ji KIM, Chang Sik KIM, Kyung Ah NAM, Hyo Young MUN, Yong Seung PARK, Yi Seul UM, Dae Sang YUN, Kwan Hee LEE, So Young LEE, Young Hoon LEE, Young Seo CHOI, Sun Young KIM, Ji Won SOHN, Do Young LEE, Seung Hoon LEE
  • Patent number: 11522068
    Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 6, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Patent number: 11371735
    Abstract: The disclosure an air conditioning system and a method of controlling the same. During the heating operation of the A2W indoor unit, the A2A valve that connects the outdoor unit to the A2A indoor unit is closed to prevent the inflow of the refrigerant into the A2A indoor unit, so it is possible to prevent performance degradation by improving performance loss due to refrigerant bypass to a stationary A2A indoor unit. In addition, in order to improve the performance due to deterioration of heating performance, the system itself can cope with a control algorithm without any additional hardware configuration, thereby minimizing the installation cost.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 28, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong Sun, Yong Sang Kong, Chang Soo Lim, Sung Jin Cho, Sung Tae Kim, Chang Seo Park, Dong Seok Bae, Kwang Nam Shin
  • Patent number: 10832966
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Publication number: 20200191423
    Abstract: The disclosure an air conditioning system and a method of controlling the same. During the heating operation of the A2W indoor unit, the A2A valve that connects the outdoor unit to the A2A indoor unit is closed to prevent the inflow of the refrigerant into the A2A indoor unit, so it is possible to prevent performance degradation by improving performance loss due to refrigerant bypass to a stationary A2A indoor unit. In addition, in order to improve the performance due to deterioration of heating performance, the system itself can cope with a control algorithm without any additional hardware configuration, thereby minimizing the installation cost.
    Type: Application
    Filed: March 21, 2018
    Publication date: June 18, 2020
    Inventors: Woong SUN, Yong Sang KONG, Chang Soo LIM, Sung Jin CHO, Sung Tae KIM, Chang Seo PARK, Dong Seok BAE, Kwang Nam SHIN
  • Publication number: 20190355832
    Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 21, 2019
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Patent number: 10453936
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Publication number: 20190259668
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Publication number: 20190131429
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Jiehui Shu, Chang Seo Park, Shimpei Yamaguchi, Tao Han, Yong Mo Yang, Jinping Liu, Hyuck Soo Yang
  • Patent number: 10184707
    Abstract: A heat pump and a control method thereof, the control method of the heat pump which heats a heated space through heat exchange between outdoor air and a refrigerant and heat exchange between the refrigerant and circulation water, includes calculating the maximum allowable frequency of a compressor based on the temperature of the outdoor air and the heating load of the heated space, calculating the mean operating frequency of the compressor while the compressor is operated at the calculated maximum allowable frequency, recalculating the maximum allowable frequency based on a result of comparison between the mean operating frequency and the maximum allowable frequency, and operating the compressor at the recalculated maximum allowable frequency, thereby improving coefficient of performance (COP) of the heat pump.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Woon Jeong, Sung Goo Kim, Chang Seo Park, Jae Hyuk Oh, Yong Hyun Jeon
  • Patent number: 9567515
    Abstract: A white light emitting device (LED) and a manufacturing method thereof wherein an LED coated with polymeric resin in which organic phosphors are solved dissolved and inorganic phosphors are dispersed creates a white LED, thereby producing an effect of excellent luminance and color coordinate without creating a compatibility problem with the polymeric resin. The present invention creates a white LED with a high luminance and a long service life using polymeric composition containing organic and inorganic phosphors, organic and inorganic combined phosphors and organosilicates, and an epoch making improvement in terms of luminance and credibility without additional process added to an existing element fabricating process, thereby enabling to achieve price competitiveness through cost reduction.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: February 14, 2017
    Assignee: LG ELECTRONICS, INC.
    Inventors: Sung Eun Lee, Hee Jung Kim, Chang Seo Park
  • Patent number: 9464112
    Abstract: Provided are small peptide fragments derived from the NF-?B p65 subunit and a pharmaceutical or cosmetic composition comprising the same. The peptides have a NF-?B inhibitory activity, through controlling the transcription-activation of NF-?B. The peptides inhibit the expressions of pro-inflammatory mediators, which are induced by NF-?B, and also inhibit the transmigration of leukocytes, thereby exhibiting an anti-inflammatory activity. Especially, the peptides have excellent inhibitory activities against dermatitis and skin aging. And also, the peptides inhibit base membrane invasion of cancer cells, thereby exhibiting an inhibitory activity against the growth and/or metastasis of cancer cells.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 11, 2016
    Assignee: KNU-INDUSTRY COOPERATION FOUNDATION
    Inventors: Jang-Hee Hahn, Chang-Seo Park, In-Young Ko, Byong-Ik Chun, Byoung-Chul Kim
  • Patent number: 9391170
    Abstract: A field-effect transistor (FET) on bulk substrate and a method of fabricating the same is discussed herein. The FET includes a dielectric layer disposed on the bulk substrate and a fin structure and a gate structure disposed on the dielectric layer. The dielectric layer includes alternating first and second dielectric regions. The fin structure includes a channel region interposed between a source region and a drain region. The gate structure is capacitively coupled to the fin structure and positioned between the source region and the drain region. Improved performance characteristics of FET is primarily achieved with the dielectric layer providing electrical isolation of the fin structure from the bulk substrate.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: July 12, 2016
    Assignee: Broadcom Corporation
    Inventor: Chang Seo Park
  • Publication number: 20150252073
    Abstract: The present invention provides small peptide fragments derived from the NF-?B p65 subunit and a pharmaceutical or cosmetic composition comprising the same. The peptides have a NF-?B inhibitory activity, through controlling the transcription-activation of NF-?B. The peptides inhibit the expressions of pro-inflammatory mediators, which are induced by NF-?B, and also inhibit the transmigration of leukocytes, thereby exhibiting an anti-inflammatory activity. Especially, the peptides have excellent inhibitory activities against dermatitis and skin aging. And also, the peptides inhibit base membrane invasion of cancer cells, thereby exhibiting an inhibitory activity against the growth and/or metastasis of cancer cells.
    Type: Application
    Filed: August 20, 2013
    Publication date: September 10, 2015
    Applicant: KNU-INDUSTRY COOPERATION FOUNDATION
    Inventors: Jang-Hee Hahn, Chang-Seo Park, In-Young Ko, Byong-Ik Chun, Byoung-Chul Kim
  • Publication number: 20150054079
    Abstract: A field-effect transistor (FET) on bulk substrate and a method of fabricating the same is discussed herein. The FET includes a dielectric layer disposed on the bulk substrate and a fin structure and a gate structure disposed on the dielectric layer. The dielectric layer includes alternating first and second dielectric regions. The fin structure includes a channel region interposed between a source region and a drain region. The gate structure is capacitively coupled to the fin structure and positioned between the source region and the drain region. Improved performance characteristics of FET is primarily achieved with the dielectric layer providing electrical isolation of the fin structure from the bulk substrate.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Broadcom Corporation
    Inventor: Chang Seo PARK
  • Publication number: 20150044313
    Abstract: Disclosed is a lactic acid bacteria culture of mung bean obtained by culturing lactic acid bacteria in a culture medium containing mung bean extract. The culture contains the mung bean extract and GABA (ϝ Aminobutyric acid), so that it exhibits effects of promoting collagen synthesis and alleviating inflammation. Accordingly, the cosmetic composition containing the culture can be usefully used as a cosmetic composition for promoting collagen biosynthesis, preventing or improving skin senescence, ant i-inflammatory and preventing or improving skin injury.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Inventors: Chang-Seo PARK, Sang-June NAM, Wang-Keun CHOI, Yu-Ryang PYUN, Hyung-Yong CHO, Seok-Cheol CHO, Moo-Chang KOOK, Chang-Woo LEE, So-Young CHUNG
  • Publication number: 20140141605
    Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Chang Seo PARK, Linus JANG, Jin CHO
  • Patent number: 8728908
    Abstract: Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 20, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chang Seo Park, William James Taylor, III, John Iacoponi