Patents by Inventor Chang Seo Park
Chang Seo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140134836Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor.Type: ApplicationFiled: November 9, 2012Publication date: May 15, 2014Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: BALASUBRAMANIAN PRANATHARTHIHARAN, CHARAN VEERA VENKATA SATYA SURISETTY, JUNLI WANG, CHANG SEO PARK, RUILONG XIE
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Patent number: 8722491Abstract: Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.Type: GrantFiled: September 5, 2012Date of Patent: May 13, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Chang Seo Park, Vimal K. Kamineni
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Patent number: 8716094Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.Type: GrantFiled: November 21, 2012Date of Patent: May 6, 2014Assignee: Global Foundries Inc.Inventors: Chang Seo Park, Linus Jang, Jin Cho
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Publication number: 20140116074Abstract: A heat pump and a control method thereof, the control method of the heat pump which heats a heated space through heat exchange between outdoor air and a refrigerant and heat exchange between the refrigerant and circulation water, includes calculating the maximum allowable frequency of a compressor based on the temperature of the outdoor air and the heating load of the heated space, calculating the mean operating frequency of the compressor while the compressor is operated at the calculated maximum allowable frequency, recalculating the maximum allowable frequency based on a result of comparison between the mean operating frequency and the maximum allowable frequency, and operating the compressor at the recalculated maximum allowable frequency, thereby improving coefficient of performance (COP) of the heat pump.Type: ApplicationFiled: October 25, 2013Publication date: May 1, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Woon JEONG, Sung Goo KIM, Chang Seo PARK, Jae Hyuk OH, Yong Hyun JEON
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Publication number: 20140065811Abstract: Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Chang Seo Park, Vimal K. Kamineni
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Publication number: 20130260548Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.Type: ApplicationFiled: April 3, 2012Publication date: October 3, 2013Applicant: GLOBALFOUNDRIES Inc.Inventor: Chang Seo Park
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Patent number: 8541286Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A first plurality of trenches is etched into the first and second layers. The first plurality of trenches is filled to form a plurality of support structures. A second plurality of trenches is etched into the first and second layers. Portions of the second layer disposed between adjacent trenches of the first and second pluralities of trenches define a plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is supported in position adjacent to the gap spaces by the plurality of support structures. The gap spaces are filled with an insulating material.Type: GrantFiled: February 17, 2012Date of Patent: September 24, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventor: Chang Seo Park
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Patent number: 8536040Abstract: Generally, the present disclosure is directed to techniques for using material substitution processes to form replacement metal gate electrodes, and for forming self-aligned contacts to semiconductor devices made up of the same. One illustrative method disclosed herein includes removing at least a dummy gate electrode to define a gate cavity, forming a work-function material in said gate cavity, forming a semiconductor material above said work-function material, and performing a material substitution process on said semiconductor material to substitute a replacement material for at least a portion of said semiconductor material.Type: GrantFiled: April 3, 2012Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Inc.Inventor: Chang Seo Park
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Publication number: 20130217204Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A first plurality of trenches is etched into the first and second layers. The first plurality of trenches is filled to form a plurality of support structures. A second plurality of trenches is etched into the first and second layers. Portions of the second layer disposed between adjacent trenches of the first and second pluralities of trenches define a plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is supported in position adjacent to the gap spaces by the plurality of support structures. The gap spaces are filled with an insulating material.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: GLOBALFOUNDRIES INC.Inventor: Chang Seo Park
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Patent number: 8431472Abstract: Methods is provided for forming a CMOS device. The method includes providing a substrate and depositing a gate stack on the substrate. The gate stack includes a gate dielectric and a dummy gate including polycrystalline silicon (polySi). The method also includes depositing a dielectric layer on the substrate after depositing the gate stack on the substrate. The method further includes substituting the dummy gate with a metal without first removing the dummy gate.Type: GrantFiled: June 30, 2011Date of Patent: April 30, 2013Assignee: Globalfoundries, Inc.Inventor: Chang Seo Park
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Patent number: 8409466Abstract: A composition comprising at least one ionized silicate mineral and water, wherein the at least one ionized silicate mineral is solvated in water, and wherein decomposition comprises an ionized germanium dioxide, its method of making, and its method of using are disclosed. While the composition is subject to a wide range of applications, it is especially suited for use in a coolant system for a combustion engine, and in particular, the coolant system for an internal combustion engine for vehicles.Type: GrantFiled: September 13, 2010Date of Patent: April 2, 2013Assignees: Bizbank, Inc., Three Castle, Inc.Inventor: Chang Seo Park
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Publication number: 20130043592Abstract: Disclosed herein are various methods of forming a replacement gate comprised of silicon and various semiconductor devices incorporation such a replacement gate structure. In one example, the method includes removing a sacrificial gate electrode structure to define a gate opening, forming a replacement gate structure in the gate opening, the replacement gate structure including at least one metal layer and a silicon-containing gate structure that is at least partially made of a metal silicide and forming a protective layer above at least a portion of the replacement gate structure.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Chang Seo Park, Jin Cho
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Publication number: 20130040450Abstract: Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Chang Seo Park, William James Taylor, JR., John Iacoponi
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Publication number: 20130005131Abstract: Methods is provided for forming a CMOS device. The method includes providing a substrate and depositing a gate stack on the substrate. The gate stack includes a gate dielectric and a dummy gate including polycrystalline silicon (polySi). The method also includes depositing a dielectric layer on the substrate after depositing the gate stack on the substrate. The method further includes substituting the dummy gate with a metal without first removing the dummy gate.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: GLOBALFOUNDRIES INC.Inventor: Chang Seo Park
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Publication number: 20120138845Abstract: A composition comprising at least one ionized silicate mineral and water, wherein the at least one ionized silicate mineral is solvated in water, and wherein decomposition comprises an ionized germanium dioxide, its method of making, and its method of using are disclosed. While the composition is subject to a wide range of applications, it is especially suited for use in a coolant system for a combustion engine, and in particular, the coolant system for an internal combustion engine for vehicles.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Applicants: THREE CASTLE, INC., BIZTANK, INC.Inventor: Chang Seo PARK
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Publication number: 20120060784Abstract: A composition comprising at least one ionized silicate mineral and water, wherein the at least one ionized silicate mineral is solvated in water, and wherein decomposition comprises an ionized germanium dioxide, its method of making, and its method of using are disclosed. While the composition is subject to a wide range of applications, it is especially suited for use in a coolant system for a combustion engine, and in particular, the coolant system for an internal combustion engine for vehicles.Type: ApplicationFiled: September 13, 2010Publication date: March 15, 2012Applicants: THREE CASTLE, INC., BITZBANK, INC.Inventor: Chang Seo PARK
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Publication number: 20120055177Abstract: An air conditioner controls supply of refrigerant so that the refrigerant is first supplied to one or more indoor units in operation from an outdoor unit, and is then supplied to a hot water generator, thereby sufficiently supplying refrigerant to the indoor units in heating operation even when the hot water generator is operated.Type: ApplicationFiled: August 26, 2011Publication date: March 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Goo Kim, Jae Hyuk Oh, Seong Je Wu, Dong Woon Jeong, Yong Hyun Jeon, Chang Seo Park
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Patent number: 8022051Abstract: Disclosed is a composition containing phosphatidylserine as an effective ingredient, and more particularly to a composition containing phosphatidylserine as an effective ingredient for protecting and improving a skin, reinforcing a skin barrier function, suppressing and alleviating an inflammatory response, treating and improving an atopic skin, activating PPAR-a promoting a differentiation of the skin, protecting the skin and preventing and improving skin aging and wrinkle. Accordingly, it is possible to protect and improve the skin from the injury due to the ultraviolet or the external stimulating material such as chemical material and to reinforce and strengthen the skin barrier function using the composition, thereby improving a general skin state.Type: GrantFiled: October 20, 2005Date of Patent: September 20, 2011Assignee: Doosan CorporationInventors: Sang-June Nam, So-Young Chung, Jeong-Jun Han, Wang-Keun Choi, Chang-Seo Park, Yun-Sik Kim, Sang-Woo Cho, Young-Ho Lee, Jin-Wook Kim, Ui-Chan Koh
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Publication number: 20110203298Abstract: A heat pump system, the operation of which is controlled using a temperature difference between a water inlet and a water outlet of a heat exchanger, exchanging heat between a refrigerant and water, and a control method thereof. The heat pump system includes temperature sensors installed on a water circulation pipe unit at water inlet and outlet sides of a heat exchanger, and heats a load to a set temperature by controlling a compressor or an expander according to a difference between temperatures sensed by the temperature sensors. Here, a temperature of water transmitted to the load is set to be greater than a target load temperature by a reference value, and if the temperature difference is smaller than a designated value, the operation of the heat pump system is stopped.Type: ApplicationFiled: February 1, 2011Publication date: August 25, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Sung Goo Kim, Jae Hyuk Oh, Dong Woon Jeong, Chang Seo Park
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Publication number: 20110006378Abstract: A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices.Type: ApplicationFiled: July 7, 2009Publication date: January 13, 2011Inventors: Muhammad Hussain, Chang Seo Park