Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; an termination region formed in the vicinity of the active region; a plurality of trenches formed in a length direction of the active region; a first conductivity type hole accumulating region formed below the channel in the active region; and a first conductivity type electric field limiting region formed in the termination region. The electric field limiting region is formed so as to at least partially cover a trench positioned at a boundary between the active region and the termination region.

Abstract: A power semiconductor device may include: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on the first semiconductor region; a third semiconductor region having the first conductivity type and formed in an upper portion of the second semiconductor region; a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region, having a gate insulating layer formed on a surface thereof, and filled with a conductive material; and a fourth semiconductor region having the second conductivity type and formed to penetrate through the second semiconductor region.

Abstract: A power semiconductor device may include: a first semiconductor layer having a first conductivity type; a second semiconductor layer formed on the first semiconductor layer, having a concentration of impurities higher than that of the first semiconductor layer, and having the first conductivity type; a third semiconductor layer formed on the second semiconductor layer and having a second conductivity type; a fourth semiconductor layer formed in an upper surface of the third semiconductor layer and having the first conductivity type; and trench gates penetrating from the fourth semiconductor layer into a portion of the first semiconductor layer and having gate insulating layers formed on surfaces thereof. The trench gates have a first gate, a second gate, and a third gate are sequentially disposed from a lower portion thereof, and the first gate, the second gate, and the third gate are insulated from each other by gate insulating films.

Abstract: There is provided a power semiconductor device, including: a first semiconductor layer of a first conductive type having a thickness of t1 so as to withstand a reverse voltage of 600V; and a second semiconductor layer of a second conductive type formed inside an upper portion of the first semiconductor layer and having a thickness of t2, wherein t1/t2 is 15 to 18.

Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer.

Abstract: A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer.

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract: Disclosed herein is a power semiconductor device, including: a drift layer formed on the first surface of the semiconductor substrate, a well layer of a first conductive type, formed on the drift layer, a trench formed to reach the drift layer through the well layer, a first electrode formed in the trench, a second conductive type of second electrode region formed on the well layer, including a first region contacting the trench in a perpendicular direction and a second region spaced apart from the trench in a parallel direction and being perpendicular to the first region, a first conductive type of second electrode region formed to contact a side surface of the second conductive type of second electrode region, and a second electrode formed on the well layer and electrically connected to the second conductive type of second electrode region and the first conductive type of second electrode region.

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.

Abstract: There is provided a semiconductor device including: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on one surface of the first semiconductor region; a third semiconductor region having a first conductivity type and formed on one surface of the second semiconductor region; a gate electrode formed in a trench penetrating through the second semiconductor region and the third semiconductor region to reach an interior of the first semiconductor region; and a hole injection unit formed between the gate electrode and the first semiconductor region.

Abstract: Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode.

Abstract: The bandpass filter according to the present invention includes a housing having a plurality of cavities, wherein said plurality of cavities are isolated from each other by partitions and wherein each said partition have a coupling window; input/output connectors formed at both ends of said housing so as to pass output signals from a transmitter; coupling loops connected to said input/output connectors so as to excite an applied signal power and to combine resonance modes; dielectric resonators installed in said cavities of said housing so as to resonate a signal power transmitted from said coupling loop to the desired frequency band, said dielectric resonators including: a first resonator group formed in both said cavities which are adjacent to said coupling loops; and a second resonator group formed in said cavities which are positioned between both said cavities which are adjacent to said coupling loops, wherein said resonators of said second resonator group are stepped resonators; a plurality of frequency