Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

Abstract: A method and system to form an image of print data includes an external device to wirelessly transmit operation commands, and an image forming device to form images of print data input by a user, the image forming device including an RF combo chip attached to an operational component mountable within the image forming device to receive the transmitted operation commands from the external device and to control the image forming device to form the images of the print data according to the received operation commands.

Abstract: An image display device for providing antireflection and electromagnetic shielding effects is disclosed. The device has a faceplate, a coating panel made of glass, a plurality of coating layers laminated on one surface of the coating panel for performing antireflection and electromagnetic shielding functions, and an adhering layer for adhering the coating panel to the faceplate. The adhering layer may be an ultraviolet curable resin.

Abstract: A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

Abstract: A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: An apparatus and method of optimizing printout speed of an image forming apparatus which allows users to set a printout speed when users are going to print a document having a plurality of pages, such that overall printout time of the document can be reduced. The apparatus to optimize a printout speed of the image forming apparatus includes a printout speed setup unit which sets a printout speed value for the image forming apparatus, and a printout speed applying unit which makes a printer engine of the image forming apparatus maintain an on-state during a time period corresponding to the printout speed value.

Abstract: Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the opposing sidewalls, where the second fins have respective exposed sidewalls protruding from the substrate. The second fins or the first fin can be removed to provide at least one fin for a multi fin FET.

Abstract: Transistors of a semiconductor device are fabricated by forming a plurality of gate electrodes on a semiconductor substrate. The gate electrodes are used as an ion implantation mask. A first impurity is ion implanted below the exposed surface of the semiconductor substrate to form first impurity regions. A second impurity is ion implanted in two directions by tilting the implantation to a predetermined angle to thereby form second impurity regions separated from the first impurity regions. The second impurity regions are formed below the channel region under the gate electrodes. The second impurity regions may overlap to provide a higher impurity concentration below a portion of the channel.

Abstract: A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.

Abstract: An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

Abstract: A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

Abstract: In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of the trench, respectively. A gate electrode filling the trench is formed. Source/drain regions are formed at portions of the substrate adjacent to the sidewall of the gate electrode. Stopper regions are formed at portions of the substrate beneath the source/drain regions and beneath the first and second threshold voltage control regions, respectively. The buried channel type transistor has a high breakdown voltage between the source/drain regions although a threshold voltage thereof is low.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.

Abstract: A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.