Abstract: A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Abstract: MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: Transistors of a semiconductor device are fabricated by forming a plurality of gate electrodes on a semiconductor substrate. The gate electrodes are used as an ion implantation mask. A first impurity is ion implanted below the exposed surface of the semiconductor substrate to form first impurity regions. A second impurity is ion implanted in two directions by tilting the implantation to a predetermined angle to thereby form second impurity regions separated from the first impurity regions. The second impurity regions are formed below the channel region under the gate electrodes. The second impurity regions may overlap to provide a higher impurity concentration below a portion of the channel.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.

Abstract: The present invention provides an integrated printer driver including a plurality of printer drivers which are produced in various types to satisfy various computer environments. The integrated printer driver automatically changes printer drivers when printing error occurs. The method for automatically changing the printer drivers comprises steps of determining the type of a printing error on occurrence, changing a preset printer driver to another appropriate printer driver of a plurality of printer drivers in a stored integrated printer driver in order to overcome the error corresponding to the determination, and setting the changed printer driver in order to enable the printer to recognize the printer driver.

Abstract: In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule.

Abstract: In the present invention, an apparatus of testing leakage current protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern composed of a length portion, multiple tooth portions which are connected orthogonally to the length portion, and vias which are formed vertically from the ends of the tooth portions, respectively, through an interlayer dielectric layer. Additionally the apparatus has a serpentine-like pattern including a length parallel part or a connection part which is running parallel to the length portion, a tooth parallel part which is parallel to the tooth portion and formed at a level different from the level of the connection part or the length parallel part, and vias connecting them. The via of the comb-like pattern is located at the central position between the neighboring two vias of the serpentine-like pattern.

Abstract: The present invention provides a data transmission/reception device capable of transmitting/receiving data between a host computer and a remote facsimile or a remote computer through an electrophotographic printer, having a ring detector for detecting a ring signal indicative of a facsimile reception; a modulator/demodulator for demodulating the data transferred from the remote facsimile or the remote computer and modulating the data supplied from the host computer connected to the printer, a control part for controlling the modulator/demodulator to start the facsimile reception if the ring has been detected, and transmitting the data demodulated by the modulator/demodulator to an engine control part for direct printing or to the host computer and transmitting the data supplied from the host computer to the modulator/demodulator for modulation and transmission to the remote facsimile or the remote computer; and an interface part for interfacing with the engine control part for enabling direct printing either

Abstract: A power control device and method capable of performing a power control of the printer in the host computer is provided. A host computer provides a power-on signal to the printer interface, which provides a power-on signal to the power control circuit which delivers DC power to the printer. The power-on signal originates either from a user input at the host computer or the flipping of a soft switch. Similarly, power to the peripheral printer may be disconnected in the same way.