Abstract: There is provided a smoke detector including a substrate, a light source and a light sensor. The light source and the light sensor are arranged adjacently on the substrate. The substrate is arranged with an asymmetric structure to cause an illumination region of the light source to deviate toward the light sensor thereby increasing a ratio of light intensity reflected by smoke with respect to reference light intensity.

Abstract: Proposed are a wafer inspection apparatus and a method of inspecting a wafer using the wafer inspection apparatus. The proposed wafer inspection apparatus includes a horizontal magnetic field generation unit arranged proximate to a lateral surface of a wafer and forming a magnetic field in such a manner that lines of magnetic force propagate in a horizontal direction, a vertical magnetic field generation unit arranged under the wafer and generating a magnetic field in such a manner that lines of magnetic force propagate in a direction vertical to the wafer, an image measurement unit arranged over the wafer and measuring an image of the wafer, and a wafer movement stage moving the wafer in a first direction and a second direction.

Abstract: The present invention relates to a film quality improver, a method of forming a thin film using the film quality improver, a semiconductor substrate fabricated using the method, and a semiconductor device including the semiconductor substrate. The present invention provides a compound having a predetermined structure as a film quality improver. According to the present invention, by forming a shielding area for a molybdenum-based thin film on a substrate, the deposition rate of a molybdenum-based thin film may be reduced, and the growth rate of a thin film may be controlled. Thus, even when forming a thin film using a solid compound on the substrate with a complicated structure at room temperature, step coverage and the thickness uniformity of the thin film may be greatly improved, and corrosion or deterioration may be prevented, thereby improving the crystallinity and electrical properties of a thin film.

Abstract: Aspects concern a. method for controlling a transport system comprising determining, for first score adjustment vectors, allocation rates, fulfilment rates and gains of fulfilled predetermined transport tasks. The method further comprises determining a second score adjustment vector from the allocation rates, fulfilment rates and gains determined for the first score adjustment vectors by estimating the second score adjustment vector to maximize a gain of fulfilled requested transport tasks subject to a predetermined minimum allocation rate of requested, transport tasks of each transport task category and a predetermined minimum fulfilment rate of requested transport tasks of each transport task category.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having an active region and an isolation region. The semiconductor structure includes gate stacks on the substrate that extend over the active region and the isolation region. The semiconductor structure includes a gate spacer on sidewalls of the gate stacks. The semiconductor structure includes an interlevel dielectric (ILD) layer over the substrate and implanted with one or more dopants, the ILD layer having a top implanted portion over a bottom nonimplanted portion. The top implanted portion seals an air gap between a sidewall of the ILD layer and the gate spacer.

Abstract: A crampon includes a crampon base for fitting to an underside of an item of footwear, such as a shoe or a boot. A harness extends from the crampon base and may be attached to the crampon base using rivets. The harness and the crampon base define a space for receiving the item of footwear. The crampon base comprises at least one cleat assembly with a cleat base embedded within the crampon base. One or more spikes extend from the cleat base.

Abstract: A light-emitting unit, having a substrate; a first light-emitting body formed on the substrate, and having a first longer side and a first shorter side; a second light-emitting body formed on the substrate, and having a second longer side and a second shorter side which is parallel to the first longer side; a third light-emitting body formed on the substrate, having a third longer side and a third shorter side which is parallel to the first longer side, and electrically connected to the first light-emitting body and the second light-emitting body; a first electrode covering the first light-emitting body and the second light-emitting body, and electrically connecting to the first light-emitting body; a second electrode separated from the first electrode, and covering the second light-emitting body without covering the first light-emitting body; and a transparent element enclosing the first light-emitting body, the second light-emitting body, and the third light-emitting body.

Abstract: Establishing a data store of content metadata includes receiving, from a content player executing on a client device, an indication of content played by the content player, the indication comprising one or more pieces of metadata associated with the content. It further includes selecting a set of one or more rules applicable to parsing the metadata associated with the content. It further includes processing the metadata at least in part by applying the selected parsing rules to at least a portion of the metadata associated with the content. It further includes storing, to a data store, at least some of the processed metadata associated with the content.

Abstract: A manufacturing method of a transistor includes at least the following steps. An insulating layer is provided. A source/drain material layer is formed on the insulating layer to cover top surface and sidewalls of the insulating layer. A portion of the source/drain material layer is removed until the insulating layer is exposed, so as to form a source region and a drain region respectively on two opposite sidewalls of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A cooking apparatus includes a cooking plate including a cooking area divided into a plurality of sub-areas; a plurality of induction heating coil groups corresponding to the plurality of sub-areas; a plurality of drive assemblies configured to supply a driving current to each of the plurality of induction heating coil groups; a user interface configured to receive a compartment command that divides the cooking area of the cooking plate into the plurality of sub-areas. The cooking apparatus includes a sub-assembly configured to determine an induction heating coil group corresponding to the sub-area in which a cooking vessel is placed when the compartment command is input; and a controller configured to control a drive assembly to supply a respective driving current to the determined induction heating coil group such that a preset target temperature is distributed to an induction heating coil overlapping the sub-area in which the cooking vessel is placed.

Abstract: A semiconductor device includes a stacked structure, a first flight of steps, a second flight of steps and a third flight of steps. The stacked structure includes a memory array. The first flight of steps, the second flight of steps and the third flight of steps are disposed at a first end of the stacked structure along a first direction. The second flight of steps disposed between the first flight of steps and the third flight of steps, and a length of the second flight of steps is less than a length of the first flight of steps and a length of the third flight of steps along the first direction.

Abstract: A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the multi-layer stack, a charge storage layer disposed between the conductive layers and the channel layer, a first conductive pillar and a second conductive pillar adjacent to the channel layer, a first interconnect structure connected to an end of the first conductive pillar, and a second interconnect structure connected to an end of the second conductive pillar. The end of the first conductive pillar connected to the first interconnect structure and the end of the second conductive pillar connected to the second interconnect structure are located on opposite sides of the multi-layer stack.

Abstract: A method of forming a device includes the following steps. A multi-layer stack is formed, wherein the multi-layer stack includes a plurality of dielectric layers and a plurality of first sacrificial layers stacked alternately. A first trench is formed in the multi-layer stack. A memory material layer is formed on a sidewall of the first trench. A channel layer is conformally on the sidewall of the first trench and over the memory material layer. A plurality of conductive pillars are formed in the first trench.

Abstract: A first conductive pillar is formed. A plurality of second conductive pillars are formed at different sides of the first conductive pillar. A plurality of dielectric pillars are respectively formed between the first conductive pillar and the plurality of second conductive pillars. A channel layer is formed to continuously surround the first conductive pillar, the plurality of second conductive pillars and the plurality of dielectric pillars. A memory material layer is formed to surround the channel layer.

Abstract: A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.