Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The memory material layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive lines respectively.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

Abstract: The present invention relates to a method for preparing superabsorbent polymer. The method for preparing superabsorbent polymer according to the present invention enables providing superabsorbent polymer having excellent absorption ratio, absorption speed and permeability.

Abstract: A cavitation reduction valve structure using a dispersion valve includes: a main valve including a front end portion to which a fluid is introduced, a rear end portion from which a fluid is discharged, and a body portion which is arranged between the front end portion and the rear end portion; a first actuator which is connected to the body portion and opens and closes the body portion and controls a flow rate passing through the body portion; a first dispersion pipe branching from the front end portion; a buffer portion which is connected to the first dispersion pipe; a second dispersion pipe connecting the buffer portion and the body portion to each other; a bypass pipe connecting the buffer portion and the rear end portion to each other; and a dispersion valve provided on the bypass pipe.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: The present invention relates to new antibody-drug conjugates (ADCs) targeting ROR1, active metabolites of such ADCs, methods for preparation of such ADCs, uses for such ADCs in treatment and/or prevention of illnesses, and uses for such ADCs in production of drugs for treatment and/or prevention of diseases, more specifically diseases associated with over-expression of ROR1, for example cancer. More specifically, the present invention relates to an antibody-drug conjugate comprising an antibody that binds to ROR1 or an antigen-binding fragment thereof, and a pharmaceutical composition comprising the same.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.

Abstract: A crampon includes a crampon base for fitting to an underside of an item of footwear, such as a shoe or a boot. A harness extends from the crampon base and may be attached to the crampon base using rivets. The harness and the crampon base define a space for receiving the item of footwear. The crampon base comprises at least one cleat assembly with a cleat base embedded within the crampon base. One or more spikes extend from the cleat base.

Abstract: A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (InxSnyTizMmOn). In formula 1, 0<x<1, 0?y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.

Abstract: A vehicular air conditioning system includes an intake case having an indoor air inlet for introducing an indoor air present in a vehicle interior and an outdoor air inlet for introducing an outdoor air present outside a vehicle, an intake door installed in the intake case to selectively block one of the outdoor air inlet and the indoor air inlet while rotating about a rotation center shaft, and a water blocking part configured to block water flowing into the vehicle interior from the indoor air inlet of the intake case.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: Modified exosomes are disclosed that include an exosome and a targeting modality that extends outwardly from a surface membrane of the exosome. Also disclosed are methods of producing and using the modified exosomes.

Abstract: The super absorbent polymer comprises: a base polymer powder including a first crosslinked polymer of a water-soluble ethylenically unsaturated monomer having at least partially neutralized acidic groups; and a surface crosslinked layer formed on the base polymer powder and including a second crosslinked polymer in which the first crosslinked polymer is further crosslinked via a surface crosslinking agent, wherein the super absorbent polymer has: a fixed height absorption (FHA) of 22.5 g/g to 29 g/g, a saline flow conductivity (SFC) of 35 (·10?7 cm3·s/g) or more, and T-20 of 180 seconds or less.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.

Abstract: A level indicating device for a tank includes: a differential pressure type level gauge configured to measure a level of a fluid in a tank on the basis of a pressure according to the level of the fluid in the tank; and a level indicator configured to indicate the level of the fluid by moving in a vertical direction according to a differential pressure signal measured by the differential pressure type level gauge.