Patents by Inventor Chang-Sup Mun

Chang-Sup Mun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8822287
    Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jung Kim, Ki-hyun Hwang, Kyung-Hyun Kim, Han-Mei Choi, Dong-Chul Yoo, Chan-Jin Park, Jong-Heun Lim, Myung-Jung Pyo, Byoung-Moon Yoon, Chang-Sup Mun
  • Patent number: 8592269
    Abstract: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyun Hwang, Won-Jun Jang, Jae-Young Ahn, Chang-Sup Mun, Jung-Hyun Park
  • Patent number: 8580648
    Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Kyung-Hyun Kim, Chang-Sup Mun, Sung-Jun Kim, Jin-I Lee
  • Publication number: 20120149185
    Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Jung Kim, Ki-Hyun Hwang, Kyung-Hyun Kim, Han-Mei Choi, Dong-Chul Yoo, Chan-Jin Park, Jong-Heun Lim, Myung-Jung Pyo, Byoung-Moon Yoon, Chang-Sup Mun
  • Publication number: 20120108048
    Abstract: A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 3, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Heun Lim, Jae Joo Shim, Hyo Jung Kim, Kyung Hyun Kim, Chang Sup Mun
  • Patent number: 8058180
    Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Won Kwon, Hyung-Ho Ko, Chang-Sup Mun, Woo-Gwan Shim, Im-Soo Park, Yu-Kyung Kim, Jeong-Nam Han
  • Publication number: 20110204427
    Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 25, 2011
    Inventors: Suk-Hun CHOI, Kyung-Hyun KIM, Chang-Sup MUN, Sung-Jun KIM, Jin-I LEE
  • Publication number: 20110053365
    Abstract: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.
    Type: Application
    Filed: November 9, 2010
    Publication date: March 3, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Hyun HWANG, Won-Jun JANG, Jae-Young AHN, Chang-Sup MUN, Jung-Hyun PARK
  • Patent number: 7745338
    Abstract: A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-hoon Cha, Chang-ki Hong, Kun-tack Lee, Woo-gwan Shim, Chang-sup Mun, Ho-wook Choi
  • Publication number: 20090023265
    Abstract: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R1—OSO3?HA+, R1—CO2?HA+,R1—PO42—(HA+)2,(R1)2—PO4—HA+, or R1—SO3—HA+ where R1 is a straight or branched hydrocarbon group of C4 to C22 and A is ammonia or amine. The etching solution provides a high etching selectivity ratio of an oxide film to a nitride film or a polysilicon film. Therefore, in a semiconductor device fabrication process such as a STI device isolation process or a capacitor formation process, when an oxide film is exposed together with a nitride film or a polysilicon film, the etching solution can be efficiently used in selectively removing only the oxide film.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 22, 2009
    Inventors: CHANG-SUP MUN, Hyung-Ho Ko, Woo-Gwan Shim, Chang-Ki Hong, Sang-Jun Choi
  • Patent number: 7435301
    Abstract: Disclosed are a cleaning solution for preventing damage of a silicon germanium layer when cleaning a semiconductor device including the silicon germanium layer and a cleaning method using the same. The cleaning solution of a silicon germanium layer includes from about 0.01 to about 2.5 percent by weight of a non-ionic surfactant with respect to 100 percent by weight of the cleaning solution, about 0.05 to about 5.0 percent by weight of an alkaline compound with respect to the cleaning solution and a remaining amount of pure water. The damage to an exposed silicon germanium layer can be prevented when cleaning a silicon substrate having a silicon germanium layer. Impurities present on the surface portion of the silicon germanium layer can be effectively removed.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Mun, Doo-Won Kwon, Hyung-Ho Ko, Chang-Ki Hong, Sang-Jun Choi
  • Publication number: 20080194110
    Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 14, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-Won Kwon, Hyung-Ho Ko, Chang-Sup Mun, Woo-Gwan Shim, Im-Soo Park, Yu-Kyung Kim, Jeong-Nam Han
  • Patent number: 7354868
    Abstract: This invention provides methods of fabricating semiconductor devices, wherein an alloy layer is formed on a semiconductor substrate to form a substrate structure, which methods include using an aqueous solution diluted ammonia and peroxide mixture (APM) to perform cleaning and/or wet etching treatment steps on the substrate structure.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: April 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Won Kwon, Hyung-Ho Ko, Chang-Sup Mun, Woo-Gwan Shim, Im-Soo Park, Yu-Kyung Kim, Jeong-Nam Han
  • Patent number: 7344999
    Abstract: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: March 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Mun, Woo-Gwan Shim, Han-Ku Cho, Chang-Ki Hong, Doo-Won Kwon
  • Publication number: 20080014752
    Abstract: A method of forming fine pitch hardmask patterns includes forming a hardmask layer on a substrate and forming a plurality of first mask patterns on the hardmask layer. A buffer layer is formed on the plurality of first mask patterns, and has an upper surface defining recesses between adjacent first mask patterns. Second mask patterns are formed within the recesses formed in the upper surface of the buffer layer. The buffer layer is partially removed to expose upper surfaces of the plurality of first mask patterns, and the buffer layer is then partially removed using the first mask patterns and the second mask patterns as an etch mask to expose the hardmask layer between the first mask pattern and the second mask pattern. Using the first mask patterns and the second mask patterns as an etch mask, the hardmask layer is etched to form hardmask patterns.
    Type: Application
    Filed: April 20, 2007
    Publication date: January 17, 2008
    Inventors: Ji-hoon Cha, Chang-ki Hong, Kun-tack Lee, Woo-gwan Shim, Chang-sup Mun, Ho-wook Choi
  • Patent number: 7309683
    Abstract: A cleaning composition comprises an alkali solution, pure water, and a surfactant represented by the following chemical formula: R1-OSO3—HA+ wherein R1 is one selected from a group consisting of a butyl group, an isobutyl group, an isooctyl group, a nonyl phenyl group, an octyl phenyl group, a decyl group, a tridecyl group, a lauryl group, a myristyl group, a cetyl group, a stearyl group, an oleyl group, a licenoleyl group and a behnyl group, and A is one selected from a group consisting of ammonia, ethanol amine, diethanol amine and triethanol amine.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: December 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Mun, Chang-Ki Hong, Sang-Jun Choi, Woo-Sung Han
  • Publication number: 20070072431
    Abstract: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 29, 2007
    Inventors: Chang-Sup Mun, Woo-Gwan Shim, Han-Ku Cho, Chang-Ki Hong, Doo-Won Kwon
  • Publication number: 20070020841
    Abstract: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 25, 2007
    Inventors: Ki-Hyun Hwang, Won-Jun Jang, Jae-Young Ahn, Chang-Sup Mun, Jung-Hyun Park
  • Publication number: 20060183297
    Abstract: Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching solution. The etching solution includes a hydrofluoric acid (HF), deionized water, and an anionic surfactant. The anionic surfactant is a compound in which an anime salt is added as a counter ion, as represented by R1—OSO3?HA+, R1—CO2?HA+, R1—PO42?(HA+)2, (R1)2—PO4?HA+, or R1—SO3?HA+ where R1 is a straight or branched hydrocarbon group of C4 to C22 and A is ammonia or amine. The etching solution provides a high etching selectivity ratio of an oxide film to a nitride film or a polysilicon film. Therefore, in a semiconductor device fabrication process such as a STI device isolation process or a capacitor formation process, when an oxide film is exposed together with a nitride film or a polysilicon film, the etching solution can be efficiently used in selectively removing only the oxide film.
    Type: Application
    Filed: May 16, 2005
    Publication date: August 17, 2006
    Inventors: Chang-Sup Mun, Hyung-Ho Ko, Woo-Gwan Shim, Chang-Ki Hong, Sang-Jun Choi
  • Publication number: 20060027252
    Abstract: The present invention provides methods of processing a substrate by contacting the substrate with an inorganic solution including an organic additive, rinsing the substrate with an organic alcohol, and rinsing the substrate with deionized water. Related substrates and devices are also disclosed.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 9, 2006
    Inventors: Chang-Sup Mun, Chang-Ki Hong, Sang-Jun Choi, Hyung-Ho Ko, Sang-Yong Kim