Patents by Inventor Chang-Tsung Pai
Chang-Tsung Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135990Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 11908516Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: GrantFiled: August 27, 2021Date of Patent: February 20, 2024Assignee: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Patent number: 11758740Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.Type: GrantFiled: April 7, 2021Date of Patent: September 12, 2023Assignee: Winbond Electronics Corp.Inventors: Chang-Tsung Pai, Chiung-Lin Hsu, Yu-Ting Chen, Ming-Che Lin, Chi-Ching Liu
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Patent number: 11653583Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a metal oxide layer including a plurality of conductive filament regions formed on the bottom electrode, and a plurality of top electrodes formed on the metal oxide layer, corresponding to the respective conductive filament regions. Each of the conductive filament regions has a bottom portion and a top portion. The width of the bottom portion is greater than that of the top portion. The conductive filament regions include oxygen vacancies, and regions other than the conductive filament regions in the metal oxide layer are nitrogen-containing regions.Type: GrantFiled: July 7, 2020Date of Patent: May 16, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Chang-Tsung Pai, Ming-Che Lin, Chi-Ching Liu, He-Hsuan Chao, Chia-Wen Cheng
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Publication number: 20230129196Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Applicant: Winbond Electronics Corp.Inventors: Chi-Ching Liu, Yu-Ting Chen, Chang-Tsung Pai, Shun-Li Lan, Yen-De Lee, Chih-Jung Ni
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Patent number: 11538525Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.Type: GrantFiled: October 6, 2021Date of Patent: December 27, 2022Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Patent number: 11362272Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.Type: GrantFiled: August 25, 2020Date of Patent: June 14, 2022Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chia-Wen Cheng, He-Hsuan Chao, Frederick Chen, Chang-Tsung Pai, Tzu-Yun Huang, Ming-Che Lin
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Publication number: 20220069209Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chia-Wen Cheng, He-Hsuan Chao, Frederick Chen, Chang-Tsung Pai, Tzu-Yun Huang, Ming-Che Lin
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Publication number: 20220068382Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: August 27, 2021Publication date: March 3, 2022Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Publication number: 20220028454Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Publication number: 20210366986Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.Type: ApplicationFiled: April 7, 2021Publication date: November 25, 2021Applicant: Winbond Electronics Corp.Inventors: Chang-Tsung Pai, Chiung-Lin Hsu, Yu-Ting Chen, Ming-Che Lin, Chi-Ching Liu
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Patent number: 11176996Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.Type: GrantFiled: May 13, 2020Date of Patent: November 16, 2021Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Patent number: 11152566Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.Type: GrantFiled: December 10, 2019Date of Patent: October 19, 2021Assignee: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Bo-Lun Wu, Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Publication number: 20210287934Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.Type: ApplicationFiled: March 12, 2020Publication date: September 16, 2021Applicant: Winbond Electronics Corp.Inventors: Chi-Ching Liu, Yu-Ting Chen, Chang-Tsung Pai, Shun-Li Lan, Yen-De Lee, Chih-Jung Ni
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Publication number: 20210175418Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.Type: ApplicationFiled: December 10, 2019Publication date: June 10, 2021Applicant: Winbond Electronics Corp.Inventors: Po-Yen Hsu, Bo-Lun Wu, Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Patent number: 11011231Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.Type: GrantFiled: April 15, 2020Date of Patent: May 18, 2021Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chang-Tsung Pai, Yu-Ting Chen, He-Hsuan Chao, Ming-Che Lin, Frederick Chen
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Publication number: 20210074356Abstract: A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.Type: ApplicationFiled: April 15, 2020Publication date: March 11, 2021Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Chang-Tsung Pai, Yu-Ting Chen, He-Hsuan Chao, Ming-Che Lin, Frederick Chen
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Publication number: 20210012839Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.Type: ApplicationFiled: May 13, 2020Publication date: January 14, 2021Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Publication number: 20210013408Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a metal oxide layer including a plurality of conductive filament regions formed on the bottom electrode, and a plurality of top electrodes formed on the metal oxide layer, corresponding to the respective conductive filament regions. Each of the conductive filament regions has a bottom portion and a top portion. The width of the bottom portion is greater than that of the top portion. The conductive filament regions include oxygen vacancies, and regions other than the conductive filament regions in the metal oxide layer are nitrogen-containing regions.Type: ApplicationFiled: July 7, 2020Publication date: January 14, 2021Inventors: Chang-Tsung PAI, Ming-Che LIN, Chi-Ching LIU, He-Hsuan CHAO, Chia-Wen CHENG
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Patent number: 10811603Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.Type: GrantFiled: February 19, 2019Date of Patent: October 20, 2020Assignee: Winbond Electronics Corp.Inventors: Bo-Lun Wu, Chang-Tsung Pai, Ming-Che Lin, Meng-Hung Lin