Patents by Inventor Chang-Tzu Wang
Chang-Tzu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150287838Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20150221632Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 9093565Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: GrantFiled: July 15, 2013Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20150137255Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: United Microelectronics Corp.Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20150129977Abstract: A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Yu-Chun CHEN, Chang-Tzu Wang, Tien-Hao Tang
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Publication number: 20150123184Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 8981488Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.Type: GrantFiled: November 6, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Yung-Ju Wen, Tien-Hao Tang, Chang-Tzu Wang
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Patent number: 8981521Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.Type: GrantFiled: August 23, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
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Publication number: 20150054132Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
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Patent number: 8963202Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.Type: GrantFiled: February 9, 2012Date of Patent: February 24, 2015Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20150014809Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: ApplicationFiled: July 15, 2013Publication date: January 15, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20150008529Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.Type: ApplicationFiled: July 8, 2013Publication date: January 8, 2015Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang
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Patent number: 8890250Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.Type: GrantFiled: December 28, 2012Date of Patent: November 18, 2014Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang
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Patent number: 8884337Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.Type: GrantFiled: April 8, 2013Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang
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Publication number: 20140300391Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.Type: ApplicationFiled: April 8, 2013Publication date: October 9, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 8817434Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.Type: GrantFiled: October 11, 2011Date of Patent: August 26, 2014Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20140183708Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chang-Tzu WANG, Yu-Chun CHEN, Tien-Hao TANG
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Publication number: 20140183596Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chang-Tzu WANG, Yu-Chun CHEN, Tien-Hao TANG
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Patent number: 8748278Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.Type: GrantFiled: October 31, 2013Date of Patent: June 10, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Mei-Ling Chao, Chien-Ting Lin
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Patent number: 8730628Abstract: An electrostatic protection circuit includes a strained transistor array, an unstrained transistor, and a control circuit. The strained transistor array has a first end electrically connected to a bias terminal. The unstrained transistor has a first end electrically connected to the bias terminal. The control circuit is electrically connected to a second end of the strained transistor array, a second end of the unstrained transistor and a ground terminal. The control circuit controls impedance between the second end of the strained transistor array and the ground terminal according to current flowing through the unstrained transistor. The electrostatic protection circuit is capable of preventing latch-up effect.Type: GrantFiled: October 26, 2011Date of Patent: May 20, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Tien-Hao Tang