Abstract: Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die.

Abstract: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

Abstract: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

Abstract: Subject matter described pertains to apparatuses and methods for operating a memory device.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract: Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

Abstract: Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die.