Patents by Inventor Chang-Won Yang

Chang-Won Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100142277
    Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.
    Type: Application
    Filed: June 29, 2009
    Publication date: June 10, 2010
    Inventors: Chang Won Yang, Cheul Hee Koo, Sam Kyu Won
  • Patent number: 7706190
    Abstract: In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Won Yang, Jong Hyun Wang, Se Chun Park
  • Publication number: 20090290431
    Abstract: A nonvolatile memory device includes a page buffer circuit. The page buffer circuit includes a memory cell area, a first bit line select unit, and a second bit line select unit. A plurality of memory cells of the memory cell area is connected by bit lines and word lines. The first bit line select unit i s connected to one or more bit lines of the memory cell area and is configured to precharge or discharge a selected bit line in response to a control signal. The second bit line select unit is connected to the same bit line as the first bit line select unit and is configured to precharge or discharge the selected bit line simultaneously with the first bit line select unit.
    Type: Application
    Filed: June 28, 2008
    Publication date: November 26, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Se Chun Park, Duck Ju Kim, Chang Won Yang
  • Publication number: 20090161443
    Abstract: A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register.
    Type: Application
    Filed: May 30, 2008
    Publication date: June 25, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Chang Won YANG, Jong Hyun Wang, Se Chun Park
  • Publication number: 20090141561
    Abstract: In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.
    Type: Application
    Filed: June 27, 2008
    Publication date: June 4, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Chang Won Yang, Jong Hyun Wang, Se Chun Park
  • Patent number: 7515476
    Abstract: A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.
    Type: Grant
    Filed: May 19, 2007
    Date of Patent: April 7, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seong Hun Park, Duck Ju Kim, Chang Won Yang
  • Patent number: 7488110
    Abstract: End-plates for linear motion sliders and linear motion sliders for use with the end-plates, particularly an end-plate for linear motion sliders and a linear motion slider for use with the end-plate, in which first and second support portions, which contact and support the outer surfaces of balls, are provided in the circumferential inner surface of the end-plate, and a space is defined between the outer surfaces of the balls and a junction surface between the first and second support portions. Therefore, the stiffness of the end-plate is increased, and the balls can stably circulate in a slider, thus reducing noise and vibration. Furthermore, the space serves to keep lubricant therein, whereby the balls can more efficiently circulate in the slider.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: February 10, 2009
    Assignee: SBC Linear Co., Ltd.
    Inventors: Jin-Kwoan Lee, Chang-Won Yang
  • Publication number: 20080205138
    Abstract: A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.
    Type: Application
    Filed: December 28, 2007
    Publication date: August 28, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jong Hyun Wang, Duck Ju Kim, Seong Hun Park, Chang Won Yang
  • Publication number: 20080158987
    Abstract: A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.
    Type: Application
    Filed: May 19, 2007
    Publication date: July 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Seong Hun PARK, Duck Ju KIM, Chang Won YANG
  • Publication number: 20070237437
    Abstract: The present invention relates to end-plates for linear motion sliders and linear motion sliders for use with the end-plates. Particularly, the present invention relates to an end-plate for linear motion sliders and a linear motion slider for use with the end-plate, in which first and second support portions, which contact and support the outer surfaces of balls, are provided in the circumferential inner surface of the end-plate, and a space is defined between the outer surfaces of the balls and a junction surface between the first and second support portions. Therefore, the stiffness of the end-plate is increased, and the balls can stably circulate in a slider, thus reducing noise and vibration. Furthermore, the space serves to keep lubricant therein, whereby the balls can more efficiently circulate in the slider.
    Type: Application
    Filed: May 22, 2006
    Publication date: October 11, 2007
    Applicant: SBC LINEAR CO., LTD.
    Inventors: Jin-Kwoan Lee, Chang-Won Yang