Patents by Inventor Chang Wu

Chang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240092318
    Abstract: An end cover assembly, an air cylinder, a tread sweeper and a railway vehicle.
    Type: Application
    Filed: October 9, 2020
    Publication date: March 21, 2024
    Inventors: Qingbing GOU, Anxu WU, Chang FENG, Yuchen ZHANG, Bo WU, Hao XU, Zichen WANG, Xun CHEN, Dongdong WANG, Meng WAN
  • Publication number: 20240095360
    Abstract: Disclosed are a RISC-V and O-CFI mechanism-based defense method and apparatus for code reuse attacks, comprising: constructing a control flow graph according to program source codes randomized in a basic block order; on the basis of the control flow graph, obtaining a boundary range of a control flow transfer branch; executing the program source codes, obtaining a target node to which each control flow is to be transferred, and analyzing each target node in combination with the boundary range so as to defend against an abnormal control flow. The present invention can identify an illegal control flow transfer with the assistance of RISC-V security hardware according to the characteristics of a program control flow itself, and effectively handle code reuse attacks, thereby enhancing the security defense capabilities of an RISC-V system.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 21, 2024
    Inventors: Yanjun WU, Chang LIU, Chen ZHAO, Jingzheng WU, Zhiqing RUI, Bin WU, Tianyue LUO
  • Publication number: 20240097005
    Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a high-k dielectric layer, a p-type work function layer, an n-type work function layer, a dielectric anti-reaction layer, and a glue layer; and a continuous metal cap over the gate structure formed by metal material being deposited over the gate structure, a portion of the anti-reaction layer being selectively removed, and additional metal material being deposited over the gate structure. A semiconductor fabrication method includes: receiving a gate structure; flattening the top layer of the gate structure; precleaning and pretreating the surface of the gate structure; depositing metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; and containing growth of the metal cap.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hang Chiu, Jui-Yang Wu, Kuan-Ting Liu, Weng Chang
  • Publication number: 20240096971
    Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Xusheng WU, Chang-Miao LIU, Ying-Keung LEUNG, Huiling SHANG, Youbo LIN
  • Publication number: 20240097520
    Abstract: An axial flux motor includes a rotor assembly and a stator assembly. The rotor assembly has magnets. The stator assembly has a circuit substrate, segmented iron cores, and a coil. The circuit substrate extends radially. The segmented iron cores are supported on the circuit substrate to be opposite to the magnet in the axial direction. Segmented iron cores arranged in the circumferential direction. A coil is sleeved on a segmented iron core. Holding seats of an insulating material correspond respectively to the segmented iron cores. A holding seat abuts with and covers a segmented iron core from both axial sides and the circumferential direction, and is used for winding the coil. The circuit substrate has slot holes. A slot hole is used for embedding and positioning a portion of a holding seat that protrudes more towards one axial side than the coil.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Keng-Chang WU, Guo-Jhih YAN, Hsiu-Ying LIN, Kuo-Min WANG
  • Patent number: 11935954
    Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu, Chien-Tai Chan
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240086601
    Abstract: A method of generating a first performance-data-library (for a standard-cell-library) includes: for each standard cell that includes multiple gates, sorting the gates into groups including searching for matched ones amongst the gates (matched gates), grouping corresponding matched gates into corresponding multiple member-gates, and (for unmatched ones of the gates having no other matched gate (unmatched gates)), grouping the unmatched gates into corresponding single-member groups; for each standard cell, generating a corresponding first volume of performance data including, for each group, discretely calculating the first volume of performance data, mapping the volume of performance data to the subject gate in the group, and, for each multimember group, mapping the volume of performance data to non-subject gates; and basing the first performance-data-library at least in part on the first volumes of performance data.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 14, 2024
    Inventors: Johnny Chiahao LI, Tzu-Hsuan HO, Pei-Wei LAO, Bing-Hsiu WU, Jerry Chang Jui KAO
  • Publication number: 20240088071
    Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Yi XU, Yu LEI, Zhimin QI, Aixi ZHANG, Xianyuan ZHAO, Wei LEI, Xingyao GAO, Shirish A. PETHE, Tao HUANG, Xiang CHANG, Patrick Po-Chun LI, Geraldine VASQUEZ, Dien-yeh WU, Rongjun WANG
  • Publication number: 20240088145
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Patent number: 11930624
    Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 12, 2024
    Assignee: THE JOY FACTORY, INC.
    Inventors: Sampson Yang, Yun-Chang Tsui, Jui-Lin Wu
  • Publication number: 20240079278
    Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Inventors: Jhih-Yong Han, Wen-Yen Chen, Yi-Ting Wu, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11923251
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 11924906
    Abstract: In a particular implementation, a method of wireless communication includes transmitting, from a first user equipment (UE) to a second UE, a radio resource control (RRC) request that includes a first discontinuous reception (DRX) preference at the first UE. The method also includes receiving, at the first UE from the second UE, a RRC setup message that includes a second DRX preference at the second UE. The method further includes transmitting, from the first UE to the second UE, a RRC setup complete message that includes an indication of a confirmed DRX cycle.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Anantharaman Balasubramanian, Sudhir Kumar Baghel, Shuanshuan Wu, Gabi Sarkis, Tien Viet Nguyen, Kapil Gulati, Chang-Sik Choi
  • Publication number: 20240071326
    Abstract: A display device and a display method thereof are provided. A sensing module senses at least one state parameter of a display unit. A control circuit stores a plurality of overdrive characteristic lookup tables, selects and calculates an overdrive lookup table according to an overdrive characteristic corresponding to the at least one state parameter and a working parameter of the display unit, and controls the display unit to display according to the overdrive lookup table.
    Type: Application
    Filed: June 16, 2023
    Publication date: February 29, 2024
    Applicant: Qisda Corporation
    Inventor: Chun-Chang Wu
  • Publication number: 20240070690
    Abstract: Disclosed are a method and a system for forecasting an agricultural product price based on signal decomposition and deep learning. The method includes: S1, obtaining price subsequences by performing a complementary ensemble empirical mode decomposition (CEEMD) on an original price sequence of agricultural products; S2, obtaining a reconstructed sequence based on the price subsequences; S3, obtaining data features of the reconstructed sequence based on the reconstructed sequence; and S4, constructing a Bi-directional Sequence to Sequence (BiSeq2seq) model, and inputting the data features of the reconstructed sequence into a CCS-Bi-directional Sequence to Sequence (CCS-BiSeq2seq) model to obtain a forecasting result.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 29, 2024
    Inventors: Xinsheng ZHANG, Runzhou WANG, Chang YANG, Yiwei HAN, Chunyang WU, Yanan LI
  • Publication number: 20240071818
    Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.
    Type: Application
    Filed: September 22, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: I-Wei Chi, Te-Chang Hsu, Yao-Jhan Wang, Meng-Yun Wu, Chun-Jen Huang
  • Patent number: 11917772
    Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 27, 2024
    Assignee: COTEK ELECTRONIC IND. CO., LTD.
    Inventors: Chun-Wei Wu, Ta-Chang Wei, Chung-Liang Tsai, Shou-Cheng Yeh
  • Patent number: D1018559
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 19, 2024
    Assignee: Shenzhen Intellirocks Tech Co., Ltd.
    Inventors: Ruixin Lin, Chang Chen, Wenlong Wu