Patents by Inventor Chang-Youn Hwang
Chang-Youn Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11310930Abstract: An electronic device according to an embodiment of the present invention comprises a front plate, a back plate facing a direction opposite to the front plate, a side member surrounding a space between the front plate and the back plate, constructed integrally with respect to the back plate, or bonded to the back plate, wherein the side member includes an outer structure constructed of a first metallic material and including at least one first surface constructing an outer surface of the side member and at least one second surface facing the space, an inner structure constructed of a second metallic material different from the first metallic material and including at least one third surface at least partially in contact with the second surface and at least one fourth surface facing the space, a touch screen display exposed through the front plate, an internal structure disposed to the space so as to be adjacent to the side member, constructed of a first polymer material, and including at least one fifth surfacType: GrantFiled: November 8, 2018Date of Patent: April 19, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung Hee Choi, Jin Ho Lee, Young Soo Jang, Yun Sung Ha, Yong Wook Hwang, Jung Hyeon Hwang, Chang Youn Hwang, Hyeon Woo Lee, Chong Kun Cho
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Patent number: 11296088Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 24, 2019Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20210204435Abstract: An electronic device according to an embodiment of the present invention comprises a front plate, a back plate facing a direction opposite to the front plate, a side member surrounding a space between the front plate and the back plate, constructed integrally with respect to the back plate, or bonded to the back plate, wherein the side member includes an outer structure constructed of a first metallic material and including at least one first surface constructing an outer surface of the side member and at least one second surface facing the space, an inner structure constructed of a second metallic material different from the first metallic material and including at least one third surface at least partially in contact with the second surface and at least one fourth surface facing the space, a touch screen display exposed through the front plate, an internal structure disposed to the space so as to be adjacent to the side member, constructed of a first polymer material, and including at least one fifth surfacType: ApplicationFiled: November 8, 2018Publication date: July 1, 2021Inventors: Byoung Hee CHOI, Jin Ho LEE, Young Soo JANG, Yun Sung HA, Yong Wook HWANG, Jung Hyeon HWANG, Chang Youn HWANG, Hyeon Woo LEE, Chong Kun CHO
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Publication number: 20190348418Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 10411014Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 15, 2016Date of Patent: September 10, 2019Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Patent number: 10153799Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.Type: GrantFiled: October 14, 2016Date of Patent: December 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang
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Publication number: 20180098448Abstract: An electronic device is provided.Type: ApplicationFiled: December 1, 2016Publication date: April 5, 2018Inventors: Seung Chang BAEK, Soon Cheol KWON, Chang Hyeok SHIN, Sung Whan YOON, Jung Hyun IM, Chang Youn HWANG, Han Gyu HWANG, Jong Chul CHOI
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Patent number: 9867298Abstract: A case frame used in various devices and a method of manufacturing the case frame are provided. The method includes forming the case frame in a shape corresponding to a product to which the case frame is applied, forming a first painting layer with a color of a material applied to a surface of the formed case frame, depositing a transparent oxide deposition layer having a refractive index on an upper portion of the first painting layer, and forming a second painting layer on an upper portion of the transparent oxide deposition layer. Accordingly, the case frame can have an excellent texture by reproducing a brightness and a color anisotropy on the basis of a viewing angle by adding only a simple manufacturing process, thereby being able to improve quality of an electronic device in general and to promote a user's desire for purchasing the device.Type: GrantFiled: August 6, 2013Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Youn Hwang, Hak-Ju Kim, Yong-Geon Lee
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Patent number: 9699926Abstract: A case for an electronic device includes an injection preform having a recess on at least one portion of a surface thereof, a deposition layer deposited on a surface of the injection preform, and a paint layer formed on the deposition layer. The deposition layer may directly contact a surface of the injection preform. A method of manufacturing a case includes injection-molding an injection preform having a recess on a surface thereof, forming a deposition layer directly contacting a surface of the injection preform, and forming a paint layer on the deposition layer.Type: GrantFiled: March 13, 2014Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Youn Hwang, Won-Tae Kim, Hak-Ju Kim, Jong-Chul Choi
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Publication number: 20170111077Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.Type: ApplicationFiled: October 14, 2016Publication date: April 20, 2017Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang
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Patent number: 9620451Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.Type: GrantFiled: April 6, 2016Date of Patent: April 11, 2017Assignee: SK Hynix Inc.Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
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Publication number: 20160329337Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 9425200Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: October 16, 2014Date of Patent: August 23, 2016Assignee: SK Hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20160225710Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.Type: ApplicationFiled: April 6, 2016Publication date: August 4, 2016Inventors: Chang-Youn HWANG, Sang-Kil KANG, Ill-Hee JOE, Dae-Sik PARK, Hae-Jung PARK, Se-Han KWON
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Patent number: 9337203Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.Type: GrantFiled: October 3, 2014Date of Patent: May 10, 2016Assignee: SK Hynix Inc.Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
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Patent number: 9306268Abstract: An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern.Type: GrantFiled: February 10, 2014Date of Patent: April 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Youn Hwang, Hak-Ju Kim, Hee-Cheul Moon, Jong-Chul Choi
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Publication number: 20150255466Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.Type: ApplicationFiled: October 3, 2014Publication date: September 10, 2015Inventors: Chang-Youn HWANG, Sang-Kil KANG, Ill-Hee JOE, Dae-Sik PARK, Hae-Jung PARK, Se-Han KWON
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Patent number: 9070583Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.Type: GrantFiled: September 12, 2011Date of Patent: June 30, 2015Assignee: HYNIX SEMICONDUCTOR INCInventor: Chang Youn Hwang
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Patent number: RE49451Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.Type: GrantFiled: December 11, 2020Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang
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Patent number: RE50182Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.Type: GrantFiled: December 8, 2022Date of Patent: October 22, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang