Patents by Inventor Chang-Youn Hwang

Chang-Youn Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200062730
    Abstract: The present disclosure relates to a novel piperidine-2,6-dione derivative and a use thereof and, more specifically, to a piperidine-2,6-dione derivative compound having a structure of a thalidomide analog. A compound of chemical formula 1 according to the present disclosure specifically binds with CRBN protein, and is involved in functions thereof. Therefore, the compound of the present disclosure can be favorably used in the prevention or treatment of leprosy, chronic graft versus host disease, an inflammatory disease, or cancer, which are caused by actions of CRBN protein.
    Type: Application
    Filed: May 11, 2018
    Publication date: February 27, 2020
    Inventors: Jong Yeon HWANG, Jae Du HA, Sung Yun CHO, Pil Ho KIM, Chang Soo YUN, Chi Hoon PARK, Chong Ock LEE, Sang Un CHOI, Joo Youn LEE, Sunjoo AHN
  • Publication number: 20200012068
    Abstract: The proposed invention relates to a camera module with an optical image stabilization function. A flexible printed circuit board (FPCB) electrically connected to an image sensor is implemented to serve as an electrical path and at the same time, serve to provide an elastic restoring force in directions of a plurality of axes, thereby further miniaturizing and lightening the camera module.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Applicant: MCNEX CO., LTD.
    Inventors: Jang Ho Lim, Jae Hoon Kim, Chang Il Jang, Jae Hun Jo, Ki Sung Yoo, Jeong Won No, Tae Youn Hwang
  • Publication number: 20190348418
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
  • Patent number: 10411014
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
  • Patent number: 10153799
    Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang
  • Publication number: 20180098448
    Abstract: An electronic device is provided.
    Type: Application
    Filed: December 1, 2016
    Publication date: April 5, 2018
    Inventors: Seung Chang BAEK, Soon Cheol KWON, Chang Hyeok SHIN, Sung Whan YOON, Jung Hyun IM, Chang Youn HWANG, Han Gyu HWANG, Jong Chul CHOI
  • Patent number: 9867298
    Abstract: A case frame used in various devices and a method of manufacturing the case frame are provided. The method includes forming the case frame in a shape corresponding to a product to which the case frame is applied, forming a first painting layer with a color of a material applied to a surface of the formed case frame, depositing a transparent oxide deposition layer having a refractive index on an upper portion of the first painting layer, and forming a second painting layer on an upper portion of the transparent oxide deposition layer. Accordingly, the case frame can have an excellent texture by reproducing a brightness and a color anisotropy on the basis of a viewing angle by adding only a simple manufacturing process, thereby being able to improve quality of an electronic device in general and to promote a user's desire for purchasing the device.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Youn Hwang, Hak-Ju Kim, Yong-Geon Lee
  • Patent number: 9699926
    Abstract: A case for an electronic device includes an injection preform having a recess on at least one portion of a surface thereof, a deposition layer deposited on a surface of the injection preform, and a paint layer formed on the deposition layer. The deposition layer may directly contact a surface of the injection preform. A method of manufacturing a case includes injection-molding an injection preform having a recess on a surface thereof, forming a deposition layer directly contacting a surface of the injection preform, and forming a paint layer on the deposition layer.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Youn Hwang, Won-Tae Kim, Hak-Ju Kim, Jong-Chul Choi
  • Publication number: 20170111077
    Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Yong Wook Hwang, Jin Ho Lee, Young Soo Jang, Jung Hyeon Hwang, Chang Youn Hwang
  • Patent number: 9620451
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
  • Publication number: 20160329337
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 10, 2016
    Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
  • Patent number: 9425200
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 23, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
  • Publication number: 20160225710
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Application
    Filed: April 6, 2016
    Publication date: August 4, 2016
    Inventors: Chang-Youn HWANG, Sang-Kil KANG, Ill-Hee JOE, Dae-Sik PARK, Hae-Jung PARK, Se-Han KWON
  • Patent number: 9337203
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Chang-Youn Hwang, Sang-Kil Kang, Ill-Hee Joe, Dae-Sik Park, Hae-Jung Park, Se-Han Kwon
  • Patent number: 9306268
    Abstract: An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Youn Hwang, Hak-Ju Kim, Hee-Cheul Moon, Jong-Chul Choi
  • Publication number: 20150255466
    Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.
    Type: Application
    Filed: October 3, 2014
    Publication date: September 10, 2015
    Inventors: Chang-Youn HWANG, Sang-Kil KANG, Ill-Hee JOE, Dae-Sik PARK, Hae-Jung PARK, Se-Han KWON
  • Patent number: 9070583
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: June 30, 2015
    Assignee: HYNIX SEMICONDUCTOR INC
    Inventor: Chang Youn Hwang
  • Publication number: 20150126013
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Application
    Filed: October 16, 2014
    Publication date: May 7, 2015
    Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
  • Publication number: 20150065209
    Abstract: A cover member and a method for manufacturing the same are provided. The cover member includes a case on at least a portion of which a material pattern is formed and a color layer formed on the material pattern provided on the case, in which a portion of the color layer is at least partially marked different from the material pattern.
    Type: Application
    Filed: May 29, 2014
    Publication date: March 5, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang-Youn HWANG, Young-Jae LEE, Kyoung-Bin HAN, Byoung-Uk YOON
  • Publication number: 20140266924
    Abstract: An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern.
    Type: Application
    Filed: February 10, 2014
    Publication date: September 18, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang-Youn HWANG, Hak-Ju KIM, Hee-Cheul MOON, Jong-Chul CHOI