Abstract: A display device includes: a blue color filter layer in a blue transmission region of an upper substrate, and including first scattering particles; a green color filter layer in a green transmission region of the upper substrate, and including second scattering particles; a red color filter layer in a red transmission region of the upper substrate; a partition wall on the upper substrate and defining a blue transmission opening, a green transmission opening, and a red transmission opening, which overlap the blue transmission region, the green transmission region, and the red transmission region, respectively; a color conversion layer including red color conversion particles and third scattering particles, and accommodated in the red transmission opening; a light emitting element layer on a lower substrate facing the upper substrate; and a filling material between the upper substrate and the lower substrate.

Abstract: An electronic device according to an embodiment of the present invention comprises a front plate, a back plate facing a direction opposite to the front plate, a side member surrounding a space between the front plate and the back plate, constructed integrally with respect to the back plate, or bonded to the back plate, wherein the side member includes an outer structure constructed of a first metallic material and including at least one first surface constructing an outer surface of the side member and at least one second surface facing the space, an inner structure constructed of a second metallic material different from the first metallic material and including at least one third surface at least partially in contact with the second surface and at least one fourth surface facing the space, a touch screen display exposed through the front plate, an internal structure disposed to the space so as to be adjacent to the side member, constructed of a first polymer material, and including at least one fifth surfac

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: An electronic device according to an embodiment of the present invention comprises a front plate, a back plate facing a direction opposite to the front plate, a side member surrounding a space between the front plate and the back plate, constructed integrally with respect to the back plate, or bonded to the back plate, wherein the side member includes an outer structure constructed of a first metallic material and including at least one first surface constructing an outer surface of the side member and at least one second surface facing the space, an inner structure constructed of a second metallic material different from the first metallic material and including at least one third surface at least partially in contact with the second surface and at least one fourth surface facing the space, a touch screen display exposed through the front plate, an internal structure disposed to the space so as to be adjacent to the side member, constructed of a first polymer material, and including at least one fifth surfac

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.

Abstract: An electronic device is provided.

Abstract: A case frame used in various devices and a method of manufacturing the case frame are provided. The method includes forming the case frame in a shape corresponding to a product to which the case frame is applied, forming a first painting layer with a color of a material applied to a surface of the formed case frame, depositing a transparent oxide deposition layer having a refractive index on an upper portion of the first painting layer, and forming a second painting layer on an upper portion of the transparent oxide deposition layer. Accordingly, the case frame can have an excellent texture by reproducing a brightness and a color anisotropy on the basis of a viewing angle by adding only a simple manufacturing process, thereby being able to improve quality of an electronic device in general and to promote a user's desire for purchasing the device.

Abstract: A case for an electronic device includes an injection preform having a recess on at least one portion of a surface thereof, a deposition layer deposited on a surface of the injection preform, and a paint layer formed on the deposition layer. The deposition layer may directly contact a surface of the injection preform. A method of manufacturing a case includes injection-molding an injection preform having a recess on a surface thereof, forming a deposition layer directly contacting a surface of the injection preform, and forming a paint layer on the deposition layer.

Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern.

Abstract: A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.

Abstract: The disclosure provides a portable terminal including an electronic device and a case disposed thereon that provides water resistant, dust resistant, and insulation for the electronic device by proper positioning of an aperture of the electronic device that uses an area of the case as an antenna. The case includes a body part that comprises a main body with a metallic portion formed of a metallic material, and an auxiliary body disposed adjacent to the metallic portion, and at least a portion of the auxiliary body is used as an antenna for transmission and reception of signals. An insulation member is disposed between the at least a portion of the auxiliary body and the main body, and a bonding layer is disposed in at least one of an area between the insulation member and at least one area of the main body, or between the insulation member and the auxiliary body.