Abstract: A method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (MD structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD structures; in a first metallization layer over the VGD structures, forming first front-side segments extending in the first direction and including one or more front-side routing (FRTE) segments; under the active regions, forming buried segment-to-source/drain structures (BVD structures); and in a first buried metallization layer under the BVD structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (BPG) segments.

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A method and system for networking of spliced building blocks, and the spliced building blocks applicable to wireless networking are provided.

Abstract: A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A device and method of operating the device are disclosed. In one aspect, a device includes receive a first bit of first input data and a plurality of second bits of second input data. The processing circuit generates a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data. The processing circuit generates a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: A single-core polarization-maintaining dispersion compensation micro-structured optical fiber comprises a fiber core, a first layer of air holes surrounding the fiber core, the cladding defects on the x-axis, the cladding defects on the y-axis, and the cladding. The air holes in the fiber cross section are arranged in the equilateral triangle lattice. Three consecutive air holes are omitted to form a solid area. This solid area is the fiber core. There are two cladding defects along the x-axis. Their centers are respectively located at the two vertices of the hexagon on the x-axis, which is formed by the fourth air hole ring from the core exclusive the central air hole. Each cladding defect along the x-axis contains 7 air holes and goes through from the core by only 1 layer of air holes. There are also two cladding defects along the y-axis.

Abstract: A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply-accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply-accumulate operation using the second portion and the third portion.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.

Abstract: A method for performing a shift last multiplication and accumulation (MAC) process. A processing circuit can multiply a first input by a first bit of a second input to obtain a first intermediate output. The processing circuit can multiply a third input by a first bit of a fourth input to obtain a second intermediate output. The processing circuit can sum the first and second intermediate outputs to obtain a first sum. The processing circuit can multiply the first input by a second bit of the second input to obtain a third intermediate output. The processing circuit can multiply the third input by a second bit of the fourth input to obtain a fourth intermediate output. The processing circuit can sum the third and fourth intermediate outputs to obtain a second sum. The processing circuit can generate an output by accumulating the first sum and the second sum.

Abstract: The invention provides a nano-silicon agglomerate composite negative electrode material of pine needle and branch-shaped three-dimensional network structure and a method for preparing the same. The nano-silicon agglomerate composite negative electrode material comprises nano-sized core particles, a nano-silicon agglomerate of pine needle and branch-shaped three-dimensional network structure growing around the nano-sized core particles, and a composite coating layer over the nano-silicon agglomerate of needles and branch-shaped three-dimensional network structure. With measurements, it is shown that the nano-silicon agglomerate composite negative electrode material, when being applied in lithium ion battery, has excellent battery charge-discharge cycle performances and rate capability, and it has an initial discharge capacity per gram of more than 2600 mAh/g, and an initial coulombic efficiency of no less than 85%.

Abstract: A dispersion-compensation microstructure fiber uses pure silica glass as the background material. It includes the core, the first-type defects, the second-type defects and the cladding. The air holes in the fiber cross section are arranged in the equilateral triangle lattice with the same adjacent air-hole to air-hole spacing. The core is formed by omitting 1 air hole. The first-type defects are formed by the 6 air holes locating at the vertices of hexagonal third-layer porous structure surrounding the core and their surrounding background material. The second-type defects are formed by the air holes in the first air-hole layer surrounding each first-type defect and their surrounding background material. The second-type defects act as the porous structure to surround the first-type defects and the fundamental defect modes, and can also combine with the first-type defects to act as the core of the second-order defect modes.

Abstract: A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N?1, and values of the second sequence decrement from N?1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.

Abstract: A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.

Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.

Abstract: A memory device and an operating method for computing-in-memory (CIM) are provided. The memory device for CIM comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit. Each of the memory banks comprises a first memory array, a first latch circuit, a second latch circuit and a local MAC circuit. The first latch circuit latches a first data from the first memory array in a first read cycle. The second latch circuit latches a second data from the first memory array in a second read cycle. The local MAC circuit performs a first stage CIM operation on a first latched data latched in the first latch circuit and the second latched data latched in the second latch circuit to provide a first stage CIM result. The global MAC circuit performs a second stage CIM operation on a plurality of first stage CIM results from the memory banks.