Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A device and method of operating the device are disclosed. In one aspect, a device includes receive a first bit of first input data and a plurality of second bits of second input data. The processing circuit generates a first output bit of output data based on the first bit of the first input data and a first bit of the plurality of second bits of the second input data. The processing circuit generates a second output bit of the output data based on the first bit of the first input data, the first bit of the plurality of second bits, and a second bit of the plurality of second bits of the second input data.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A mobile device may be configured to perform concurrent Satellite Positioning System (SPS) operation and wireless communications when uplink signals transmitted by the mobile device interferes with the reception of SPS signals in one or more frequency bands. The mobile device may determine if the SPS receiver has already acquired SPS signals and is in a tracking state. If the SPS receiver is not in a tracking state, an SPS acquisition procedure is initiated before the wireless communication session is initiated. The SPS acquisition procedure is performed until the SPS receiver reaches a tracking state, or until a timeout is reached. Once the SPS receiver is in a tracking state, the wireless communication session may be initiated, during which the SPS receiver is controlled, e.g., to perform signal blanking, measurement exclusion, or disable SPS reception, to mitigate interference with SPS signals.

Abstract: A method for a three-dimensional temperature and salinity field, including: based on multi-source marine environmental data, analyzing the spatiotemporal distribution characteristics of marine dynamic environmental elements, and studying the characteristics of the temperature-salinity relation; on the basis of analysis of the spatiotemporal characteristics and study of the characteristics of the temperature-salinity relation, establishing a statistical prediction model of marine environmental dynamic elements by a spatiotemporal empirical orthogonal function method; based on the observation data of temperature and salinity obtained by the marine transportation platform, correcting a marine environment forecast field around the marine transportation platform by using a realtime analysis technology of a marine environment field; and adjusting the salinity using a temperature-salinity relation curve after the temperature and salinity are forecasted.

Abstract: A mycovirus-induced gene silencing vector and a construction method and an application thereof are provided. A nucleotide sequence of the mycovirus-induced gene silencing vector is shown in SEQ ID NO: 2, and construction method for the mycovirus-induced gene silencing vector includes: (1) connecting three single-stranded circular DNA molecules DNA-A, DNA-B and DNA-C of the mycovirus FgGMTV1/HB58 in series and introducing them into a same vector to construct a recombinant vector; and (2) carrying out a deletion mutation on a coding protein p26 of the DNA-C molecule in the recombinant vector to obtain the mycovirus-induced gene silencing vector.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: An atomizer includes: an airflow channel for delivering aerosol; and two atomization cores provided in the airflow channel, each atomization core of the two atomization cores having an atomization surface, the atomization surfaces of the two atomization cores being provided oppositely. The atomization surfaces of the atomization cores are not perpendicular to a central axis of the atomizer.

Abstract: A mycovirus-induced gene silencing vector and a construction method and an application thereof are provided. A nucleotide sequence of the mycovirus-induced gene silencing vector is shown in SEQ ID NO: 2, and construction method for the mycovirus-induced gene silencing vector includes: (1) connecting three single-stranded circular DNA molecules DNA-A, DNA-B and DNA-C of the mycovirus FgGMTV1/HB58 in series and introducing them into a same vector to construct a recombinant vector; and (2) carrying out a deletion mutation on a coding protein p26 of the DNA-C molecule in the recombinant vector to obtain the mycovirus-induced gene silencing vector.

Abstract: In some implementations, an optical isolator core includes a Faraday rotator and a plurality of birefringent crystal plates. The plurality of birefringent crystal plates may include a first birefringent crystal plate to separate input light into light having a first polarization and light having a second polarization, and a second birefringent crystal plate to combine the light having the first polarization and the light having the second polarization in output light that is laterally displaced by the single stage optical isolator. The Faraday rotator may be provided between the first birefringent crystal plate and the second birefringent crystal plate. In some implementations, the plurality of birefringent crystal plates further include a third birefringent crystal plate provided between the Faraday rotator and the second birefringent crystal plate.

Abstract: In devices with flexible displays, multilayer adhesive stacks may be included. A multilayer adhesive may attach a flexible display panel to the display cover layer in an electronic device. Including multiple layers of adhesive in the adhesive stack (as opposed to a single layer) provides more degrees of freedom for the tuning and optimization of the properties of the adhesive stack. The multilayer adhesive stack therefore has better performance than if only a single layer of adhesive is used. The multilayer adhesive stack may include one or more layers of soft adhesive, hard adhesive, hard elastomer, hard polymer, and/or glass to optimize the mechanical and optical performance of the multilayer adhesive stack. Soft adhesive layers may be included to optimize lateral decoupling (e.g., during folding and unfolding) of the adhesive stack. Harder layers may be included to provide rigidity and prevent denting during impact events.

Abstract: A single-core polarization-maintaining dispersion compensation micro-structured optical fiber comprises a fiber core, a first layer of air holes surrounding the fiber core, the cladding defects on the x-axis, the cladding defects on the y-axis, and the cladding. The air holes in the fiber cross section are arranged in the equilateral triangle lattice. Three consecutive air holes are omitted to form a solid area. This solid area is the fiber core. There are two cladding defects along the x-axis. Their centers are respectively located at the two vertices of the hexagon on the x-axis, which is formed by the fourth air hole ring from the core exclusive the central air hole. Each cladding defect along the x-axis contains 7 air holes and goes through from the core by only 1 layer of air holes. There are also two cladding defects along the y-axis.

Abstract: Disclosed is a seepage and internal erosion test apparatus for geotechnical centrifuges. The apparatus includes a mounting base, a four-motorized-jack synchronized lifting table fixed onto the mounting base, a downstream water sink, a plurality of permeameters, a centrifugal pump, and an upstream water sink fixedly mounted on the four-motorized-jack synchronized lifting table; the downstream water sink, the plurality of permeameters, the centrifugal pump, and the upstream water sink are connected by means of pipes; electric ball valves are separately disposed on each branch on which the permeameter is mounted; a temperature control module and flow meters are disposed of in the pipe for connecting the upstream outlet to the permeameter water inlet.

Abstract: A method for flexible bank addressing in digital computing-in-memory (DCIM). The method includes providing bank groups, each of the bank groups comprising a respective number of memory banks, each memory bank configured to store a corresponding portion of input feature map data. The method includes reading, during a first clock cycle, a first portion of the input feature map data from a first one of the bank groups and a second portion of the input feature map data from a second one of the bank groups. The method includes performing a first multiply-accumulate operation using the first portion and the second portion. The method includes reading, during a second clock cycle, a third portion of the input feature map data from the first bank group. The method includes performing a second multiply-accumulate operation using the second portion and the third portion.

Abstract: A method for collaborative controlling networks resilience of an unmanned cluster system a computer terminal and a computer readable storage media thereof are invented. The method includes: collecting both targets for tracking and the spatial status information of each unmanned system in the unmanned cluster system; establishing a kinematic model of the unmanned cluster system and constructing a dynamic model of each unmanned system accordingly; constructing an uncertainty boundary function and a adaptive robust controller of each unmanned system accordingly. Then it can effectively deal with the uncertainty of system parameters and the influence of network attack input of the unmanned cluster system by the present invention.

Abstract: A method of improving grinding, grading and capacity of ores by reducing a fineness content ratio ?0 in settled ores includes providing a two-stage ore grinding and grading system including a first fully closed circuit including a grinder and a hydrocyclone, or a two-stage ore grinding and grading system including a first-stage open circuit, and controlling parameters for ore grinding and grading as follows: controlling a dc an value of a point B on a separation cone of a second-stage ?500 mm hydrocyclone; controlling a fineness content ratio ?0 in settled ores; controlling a second-stage ore grinding and grading load Q2; and acquiring a first-stage grinding, grading and capacity Q of ores.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A display apparatus is provided. The display apparatus includes a display panel having a display portion, a connecting portion, and a bending portion; a main support layer; and an auxiliary support layer including a main portion and a folded-back portion connected to the main portion as a unitary structure. An edge portion of the display apparatus includes a stacked structure. The stacked structure includes the connecting portion; the folded-back portion on the connecting portion; at least a part of the main portion on a side of the folded-back portion away from the connecting portion; a part of the main support layer; and a part of the display portion on a side of the part of the main support layer away from the main portion. Layers of the stacked structure is curved toward a back side of the display apparatus.

Abstract: A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.