Abstract: A device including: a first adder having first adder inputs and first adder outputs; a first register having first register inputs and first register outputs, the first register inputs coupled to the first adder outputs; a second register having second register inputs and second register outputs, the second register inputs coupled to the first adder outputs; and a second adder having second adder inputs and second adder outputs and configured to receive register output signals from the first register outputs and the second register outputs. Wherein, the first adder is configured to calculate a first sum of a first input value and a second input value, and the first register is configured to store the first sum, and the first adder is configured to calculate a second sum of a third input value and a fourth input value, and the second register is configured to store the second sum.

Abstract: A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.

Abstract: A polarization-maintaining dispersion-compensation microstructure fiber includes an inner core, an air-hole array in area 1 and an air-hole array in area 2. The air holes in the area 1 and 2 air-hole arrays are arranged in square lattice. The air-hole arrays in areas 1 and 2 are dislocated by half-layer along y-direction. In area 1, 2 air holes in the middle row are omitted to form a solid area as the inner core. 2 outer cores are located in 2 sub-areas of area 2, and each outer core contains 2 air holes. The long (or short) axes of the inner and outer cores are perpendicular, and the center points of the inner core and the two outer cores are located on the x-axis. The optical mode has a large negative dispersion in a certain polarized direction of the inner core, and the microstructure fiber can maintain the polarized direction of this mode during transmission.

Abstract: A circuit includes a data register configured to receive a signal including a plurality of data elements, a first selection circuit coupled to the data register, a counter, a second selection circuit coupled to the counter, and an inverter coupled between the counter and the second selection circuit. The data register outputs a plurality of bits of each data element to the first selection circuit, the counter and the inverter generate complementary signals in which sequential data elements have cyclical values that step in opposite directions, the second selection circuit alternatively outputs each of the complementary signals as a selection signal to the first selection circuit, and the first selection circuit, responsive to the selection signal, outputs the pluralities of bits of the data elements in alternating sequential orders.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

Abstract: A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second r

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

Abstract: A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second r

Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.

Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.