Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: An electronic package is provided in the present disclosure. The electronic package comprises: an electronic component; a thermal conductive element above the electronic component, wherein thermal conductive element includes a first metal; an adhesive layer between the electronic component and the thermal conductive element, wherein the first adhesive layer includes a second metal; and an intermetallic compound (IMC) between the first metal and the second metal.

Abstract: Ophthalmic compositions including compatible solute components and/or polyanionic components are useful in treating eyes, for example, to relieve dry eye syndrome, to protect the eyes against hypertonic insult and/or the adverse effects of cationic species on the ocular surfaces of eyes and/or to facilitate recovery from eye surgery.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: There is provided an imaging system including a camera and a control host. The camera identifies ambient light intensity and performs trigger event detection in a low power mode. When the camera detects a trigger event in the low power mode, the control host is woken up. The camera also determines an exposure mode according the ambient light intensity and informs the exposure mode to the control host such that an operating mode of the control host after being woken up matches the exposure mode of the camera.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

Abstract: A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species in the amorphous region, and performing a second implantation process to implant a second species in the amorphous region. The second species includes fluorine, nitrogen, or carbon. The method further includes performing an annealing process to recrystallize the amorphous region.

Abstract: Source/drain fabrication methods for stacked device structures are disclosed herein. An exemplary method for forming a source/drain stack may include a frontside process and a backside process. The frontside process may include forming a frontside source/drain trench, forming a dummy source/drain in the frontside source/drain trench, and forming an upper source/drain in the frontside source/drain trench over the dummy source/drain. The backside process may include exposing a backside of the dummy source/drain, removing (partially or completely) the dummy source/drain to form a backside source/drain trench, and forming a lower source/drain in the backside source/drain trench. The dummy source/drain may be formed of semiconductor material or dielectric material, and a portion of the dummy source/drain may remain between the upper source/drain and the lower source/drain.

Abstract: A memory management circuit, an electronic device and a memory management method are provided. The memory management circuit includes a controller and an address mapping logic. The controller records addresses of available storage spaces within a memory device, wherein a searching logic of the controller stores the addresses in a storage device, and the addresses are queued with a specific order in the storage device. When a computing circuit send a storage request to request for a storage resource, the searching logic obtains at least one address queued in the storage device according to the specific order of the addresses queued in the storage device, to accordingly generate a mapping table, and the address mapping logic performs an address mapping operation upon the storage request according to the mapping table, to allow the computing circuit to utilize the available storage spaces according to the mapping table.

Abstract: An unmanned aerial device includes a body, a heat-generating assembly, and a propulsion assembly. The body has a head end, an airflow guide space, and a tail end. The head end is opposite to the tail end, and the airflow guide space is located between the head end and the tail end. The head end has an air intake, and the tail end has an exhaust vent. The airflow guide space is communicated with the air intake and the exhaust vent. The heat-generating assembly is disposed in the airflow guide space. The propulsion assembly is connected to the tail end, and the propulsion assembly is adapted to generate a propulsion airflow through the air intake, the heat-generating assembly, and the exhaust vent.

Abstract: An electronic device is provided by the present disclosure. The electronic device includes a substrate, an electronic component, and a bonding structure. The bonding structure is disposed between the electronic component and the substrate, and the bonding structure includes at least a first bonding layer and at least one compressible layer.

Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Abstract: A smart ring with a physiological feature detecting method is applied to a target object. The smart ring includes a pressure sensor and an operation processor. The pressure sensor is adapted to detect a pressure value of the target object applied for the smart ring. The operation processor is electrically connected with the pressure sensor, and adapted to compare the pressure value with a preset condition and determine a behavior of the target object according to a comparison result of the pressure value and the preset condition for generating a related operation command.

Abstract: A an electric deck frame structure (1, 1A) includes: corner lifting vertical posts (10), each having a carrying seat (11) and a retractable rod (12), the carrying seat includes a first connection part (111) having a first electric connection assembly (1133) and a second connection part (116) having a second electric connection assembly (1183); connection pipes (20), connected to the corner lifting vertical posts (10) and having a first opening (21) and a second opening (22); a transformer (30) having an electricity input port (31) arranged corresponding to the first opening (21) and an electricity output port (32) arranged corresponding to the second opening (22), the transformer is hidden in the connection pipe, and a power and signal main cable (40), connected to the electricity output port (32), the first electric connection assembly (1133) and the second electric connection assembly (1183).

Abstract: A wearable device is provided. The wearable device includes an electronic component and an encapsulant. The encapsulant includes a low-penetrability region encapsulating the electronic component and a high-penetrability region physically separated from the electronic component.

Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.