Patents by Inventor Changging LIN

Changging LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240410453
    Abstract: A linear actuator (1) with the protection mechanism includes: a motor case (10) having a case member (11) with a bottom plate (111) on which a through hole (114) is formed; a drive mechanism (20) accommodated in the case member (11); a transmission mechanism (30) having a machine core (31), a bearing (32), a base seat (33) with an extending plate (332) on which a penetrated hole (333) is formed, and a fasten unit (34) with a head part (341), the machine core (31) is connected to the drive mechanism (20), the bearing (32) is disposed on the base seat (33) and sheathes the machine core (31), the fasten unit (34) is fastened with the bottom plate (111); and a protection structure (40) sheathing the fasten unit (34) and disposed between the bottom plate (111) and the head part (341).
    Type: Application
    Filed: May 3, 2024
    Publication date: December 12, 2024
    Inventor: Yu-Chang LIN
  • Publication number: 20240407598
    Abstract: A casing of an oven includes a base, two first plates and two second plates. The base has two first pivot portions and two second pivot portions. Two first axes and two second axes are defined. Each of the two first axes passes through one of the two first pivot portions. Each of the two second axes passes through one of the two second pivot portions. Each of the two first axes and the two second axes re spaced apart from one another in a height direction of the base. Each of the two first plates is pivotally connected to one of the two first pivot portions. Each of the two second plates is pivotally connected to one of the two second pivot portions. As the four axes are respectively located at different positions in the height direction of the base, the two first plates could be stacked and the two second plates could be stacked upon folding the casing.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: GRAND MATE CO., LTD.
    Inventors: CHIN-YING HUANG, HSIN-MING HUANG, HSING-HSIUNG HUANG, YEN-JEN YEH, CHIEN-CHANG LIN
  • Publication number: 20240395859
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Zhi-Chang LIN, Chien Ning YAO, Shih-Cheng CHEN, Jung-Hung CHANG, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240395883
    Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.
    Type: Application
    Filed: June 15, 2023
    Publication date: November 28, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ta-Wei Chiu, Ping-Hung Chiang, Chia-Ling Wang, Wei-Lun Huang, Chia-Wen Lu, Yueh-Chang Lin
  • Patent number: 12154996
    Abstract: The present disclosure provides a photo sensing device and a method for forming a photo sensing device. The photo sensing device includes a substrate, a photosensitive member, a superlattice layer and a diffusion barrier structure. The substrate includes a silicon layer at a front surface. The photosensitive member extends into and at least partially surrounded by the silicon layer, wherein an upper portion of the photosensitive member protruding from the silicon layer has a top surface and a facet tapering toward the top surface. The superlattice layer is disposed between the photosensitive member and the silicon layer. The diffusion barrier structure is disposed at a first side of the photosensitive member and a bottom of the diffusion barrier structure is at a level below a top surface of the silicon layer, wherein at least a portion of the diffusion barrier structure is laterally surrounded by the silicon layer.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chan-Hong Chern, Weiwei Song, Chih-Chang Lin, Lan-Chou Cho, Min-Hsiang Hsu
  • Patent number: 12153280
    Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a fixed portion, a movable portion, a driving assembly and a circuit assembly. The fixed portion has a main axis and a polygonal structure surrounding the main axis. The movable portion is configured to connect an optical member, and is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The circuit assembly is electrically connected to the driving assembly.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 26, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Yen-Cheng Chen, Meng-Ting Lin, Guan-Bo Wang, Sheng-Chang Lin, Sin-Jhong Song
  • Publication number: 20240387279
    Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Yen-Chun Huang, Shu Ling Liao, Fang-Yi Liao, Yu-Chang Lin
  • Publication number: 20240387738
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
  • Publication number: 20240387273
    Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng CHING, Zhi-Chang LIN, Shi Ning JU, CHIH-HAO WANG, Kuan-Ting PAN
  • Publication number: 20240388025
    Abstract: The connector assembly for a seat belt comprises a wire-end connector and a board-end connector. The wire-end connector and the board-end connector are respectively designed to form an integral structure of the shell and internal components using stoppers and hooks. When the wire-end connector is fitted with the board-end connector in a fitting direction, they are engaged with each other, thereby preventing relative movement in the fitting direction. The connector assembly further includes a multi-level waterproof design for preventing the connector assembly and the circuit board from moisture damage.
    Type: Application
    Filed: January 9, 2024
    Publication date: November 21, 2024
    Inventors: Hsien-Chang LIN, Chun-Wei CHANG
  • Publication number: 20240385399
    Abstract: A connector module capable of transmitting display data signals includes first and second light-emitting devices, a module connector including first and second terminals, and first and second optical transceivers respectively including at least one electrical-optical converting circuit and at least one optical-electrical converting circuit. One of the at least one electrical-optical converting circuit of the first optical transceiver is electrically coupled to the first light-emitting device and the first terminal, and one of the at least one electrical-optical converting circuit of the second optical transceiver is electrically coupled to the second light-emitting device and the second terminal. A portion of the at least one optical-electrical converting circuit of the first optical transceiver is electrically isolated to any optoelectronic device and the module connector.
    Type: Application
    Filed: March 20, 2024
    Publication date: November 21, 2024
    Inventors: Chang-Lin Hsieh, Che-Fu Liang, Shih-Jou Huang, Kun-Yin Wang
  • Publication number: 20240387700
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.
    Type: Application
    Filed: July 27, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chang Lin, Liang-Yin Chen, Chun-Feng Nieh, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12148672
    Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Shu Ling Liao, Fang-Yi Liao, Yu-Chang Lin
  • Publication number: 20240379855
    Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240379803
    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei Ju LEE, Zhi-Chang LIN, Chun-Fu CHENG, Chung-Wei WU, Zhiqiang WU
  • Publication number: 20240379751
    Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chang Lin, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240380804
    Abstract: The present disclosure relates to a system and a method for playlist generation. The method includes: obtaining a first stream portion information and a unique key from a first streaming server; determining a first set of stream portions stored on a space of a cloud server to be consistent with the first stream portion information, the space being addressable by the unique key; generating a playlist file according to the first stream portion information; obtaining a second stream portion information and the unique key from a second streaming server; determining a second set of stream portions stored on the space of the cloud server to be consistent with the second stream portion information; and updating the playlist file according to the second stream portion information.
    Type: Application
    Filed: September 18, 2023
    Publication date: November 14, 2024
    Inventors: Kun-Ze LI, Che-Wei LIU, You-Chang LIN
  • Publication number: 20240377586
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiwei Song, Chan-Hong CHERN, Chih-Chang LIN, Stefan RUSU, Min-Hsiang HSU
  • Publication number: 20240379875
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess and a second S/D recess. The method includes forming a first bottom layer in the first S/D recess and a second bottom layer in the second S/D recess, and forming a first dielectric liner layer over the first bottom layer. The method includes forming a first top layer over the first dielectric liner layer, and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien-Ning YAO, Tsung-Han CHUANG, Kai-Lin CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240379663
    Abstract: An integrated circuit includes a substrate, a well formed over a portion of the substrate, a stacked structure formed over a first portion of the well, a doped epi structure formed over a second portion of the well adjacent the stacked structure and below a plane defined by an upper surface of the first portion of the well, and a source/drain region formed over the doped epi structure.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: Yu-Chang LIN, Liang-Yin CHEN, Huicheng CHANG, Yee-Chia YEO