Patents by Inventor Changlin ZHAO

Changlin ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200397319
    Abstract: A wearable apparatus and a method of adjusting the same, wherein the wearable apparatus comprises: a determining circuit configured to determine whether the wearable apparatus has been switched to a preset operating mode; an adjusting circuit configured to adjust the wearable apparatus to satisfy an operating requirement of a current operating mode when the determining circuit determines that the wearable apparatus has been switched to the preset operating mode.
    Type: Application
    Filed: March 25, 2019
    Publication date: December 24, 2020
    Inventors: Zifeng WANG, Yan REN, Lei CAO, Kai ZHAO, Junmin SUN, Changlin LENG
  • Patent number: 10867969
    Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 15, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Publication number: 20200333564
    Abstract: An optical imaging lens includes first, second, third, fourth, fifth and sixth lens elements arranged in order from the object side to the image side along an optical axis. The first lens element has negative refractive power. The object-side surface of the fourth lens element has a convex part in a vicinity of a periphery of the fourth lens element. The image-side surface of the sixth lens element has a convex part in a vicinity of a periphery of the sixth lens element. The effective focal length of the optical imaging lens is EFL, and a sum of all air gaps from the first lens element to the sixth lens element along the optical axis is AAG, and EFL and AAG satisfy 0.9?EFL/AAG?2.6.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Applicant: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Shih-Han Chen, Huabin Liao, Changlin Zhao
  • Publication number: 20200333563
    Abstract: An optical imaging lens includes first, second, third, fourth, fifth and sixth lens elements arranged in order from the object side to the image side along an optical axis. The object-side surface of the first lens element has a convex portion in a vicinity of a periphery of the first lens element. The second lens element has negative refractive power. The object-side surface of the second lens element has a convex portion in a vicinity of a periphery of the second lens element. The image-side surface of the fifth lens element has a concave portion in a vicinity of the optical axis. The image-side surface of the sixth lens element has a concave portion in a vicinity of the optical axis.
    Type: Application
    Filed: May 4, 2020
    Publication date: October 22, 2020
    Applicant: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Shih-Han Chen, Huabin Liao, Changlin Zhao
  • Publication number: 20200300082
    Abstract: The invention discloses a calculation method for dynamic fluid loss of acid-etched fracture considering wormhole propagation, which is applied to pad acid fracturing process, comprising the following steps: Step 1: dividing the construction time T of injecting acid fluid into artificial fracture into m time nodes at equal intervals, then the time step ?t=T/m and tn=n?t, where, n=0, 1, 2, 3, . . . , m, and to is the initial time; Step 2: calculating the fluid loss velocity vl(0) in the fracture at t0; Step 3: calculating the flowing pressure distribution P(n) in the fracture at tn; Step 4: calculating the width wa(n) of acid-etched fracture at tn; Step 5: calculating the wormhole propagation and the fluid loss velocity vl(n) at tn; Step 6: substituting the fluid loss velocity vl(n) into Step 3, and repeating Step 3 to Step 6 in turn until the end of acid fluid injection.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicants: SOUTHWEST PETROLEUM UNIVERSITY, PETROCHINA COMPANY LIMITED
    Inventors: Pingli Liu, Xiang Chen, Heng Xue, Honglan Zou, Liqiang Zhao, Nianyin Li, Daocheng Wang, Zhifeng Luo, Juan Du, Chong Liang, Mingyue Cui, Fei Liu, Changlin Zhou, Rong Zeng
  • Patent number: 10784163
    Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Tian Zeng, Changlin Zhao
  • Publication number: 20200286861
    Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Changlin ZHAO, Tian ZENG
  • Patent number: 10700042
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Patent number: 10684451
    Abstract: An optical imaging lens includes first, second, third, fourth, fifth and sixth lens elements arranged in order from the object side to the image side. The object-side surface of the fourth lens element has a convex portion in a vicinity of a periphery of the fourth lens element. The fifth lens element has negative refractive power. The effective focal length of the optical imaging lens EFL and the sum of all air gaps from the first lens element to the sixth lens element along the optical axis AAG of the optical imaging lens satisfies the relation: 0.9?EFL/AAG?2.6.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 16, 2020
    Assignee: Genius Electronic Optical (Xiamen) Co., Ltd.
    Inventors: Shih-Han Chen, Huabin Liao, Changlin Zhao
  • Publication number: 20200110246
    Abstract: An optical imaging lens includes first, second, third, fourth, fifth and sixth lens elements arranged in order from the object side to the image side. The object-side surface of the fourth lens element has a convex portion in a vicinity of a periphery of the fourth lens element. The fifth lens element has negative refractive power. The effective focal length of the optical imaging lens EFL and the sum of all air gaps from the first lens element to the sixth lens element along the optical axis AAG of the optical imaging lens satisfies the relation: 0.9?EFL/AAG?2.6.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 9, 2020
    Inventors: Shih-Han Chen, Huabin Liao, Changlin Zhao
  • Publication number: 20200075411
    Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.
    Type: Application
    Filed: December 28, 2018
    Publication date: March 5, 2020
    Inventors: Tian ZENG, Changlin ZHAO
  • Publication number: 20200075552
    Abstract: A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.
    Type: Application
    Filed: April 24, 2019
    Publication date: March 5, 2020
    Inventors: Changlin ZHAO, Tianjian LIU
  • Publication number: 20200075483
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a first opening and a second opening are vertically separated, and are no longer restricted by the condition that a deep upper opening needs to be filled with a thick photoresist when a TSV nested hole in vertical communication forms a middle opening and lower opening, thereby satisfying devices with different thicknesses requirements. The design is no longer restricted by the lateral process of the TSV nested hole, thereby enhancing the flexibility of the design. In the photolithography process, the deep hole does not need to be filled with the photoresist, the photoresist does not need to be thick, thereby reducing the complexity of the photolithography process and improving the exposure effect. The first metal layer and the second metal layer are directly led out via a first trench, thereby simplifying the process and reducing the production cost.
    Type: Application
    Filed: April 29, 2019
    Publication date: March 5, 2020
    Inventors: Yu ZHOU, Tianjian LIU, Sheng HU, Changlin ZHAO, Xing HU
  • Publication number: 20200075549
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 5, 2020
    Inventors: Changlin ZHAO, Tian ZENG
  • Publication number: 20200075460
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In the device, the isolation layer is used to prevent the first metal layer and the second metal layer which are over-etched and back-splashed from diffusing to a first substrate; and the isolation layer serves as a barrier layer to prevent an interconnection layer from diffusing into the first substrate. Further, the isolation layer includes a silicon nitride layer, which is advantageous for preventing the metal layers from back-splashing and diffusing to the sidewall of the first substrate. The isolation layer further includes a first silicon oxide layer and a second silicon oxide layer, wherein the second silicon oxide layer is used to protect the silicon nitride layer from being etched and consumed and the first silicon oxide layer is used to improve the adhesion between the silicon nitride layer and the first substrate.
    Type: Application
    Filed: April 29, 2019
    Publication date: March 5, 2020
    Inventors: Xing Hu, Yu Zhou, Tianjian Liu, Sheng Hu, Changlin Zhao
  • Publication number: 20200009763
    Abstract: A thermal extrusion method to fabricate large-dimension superhydrophobic cylinder pillar arrays with droplet pancake bouncing phenomenon. Preparing thermal extrusion mold: the through-hole arrays with 0.8˜1.25 mm diameter, 0.25 mm interval space and 0.6˜1.0 mm height are first obtained on metals, and are then polished, rinsed and dried. Thermal extrusion: polymer materials are first thermally extruded on the obtained mold and cooled to room temperature. Demold: excess polymer materials flowing from the through hole are cut off and then the polymer cylinder pillar arrays are lifted off from the mold. Superhydrophobic treatment: the whole polymer sample is treated using mixed liquid spray consisting of titanium oxide nanoparticles dispersed in fluoroalkylsilane ethanol solution, and the superhydrophobic cylinder pillar arrays are obtained.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 9, 2020
    Inventors: Jinlong SONG, Liu HUANG, Changlin ZHAO, Mingqian GAO, Xin LIU
  • Patent number: 10473898
    Abstract: An optical imaging lens includes first, second, third, fourth, fifth and sixth lens elements arranged in order from the object side to the image side. The first lens element has an image-side surface with a concave portion in a vicinity of its periphery, the third lens element has positive refractive power and an object-side surface with a convex portion in a vicinity of its periphery, the fifth lens element has negative refractive power, and the sixth lens element has an image-side surface with a concave portion in a vicinity of the optical axis.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Genius Electronic Optional (Xiamen) Co., Ltd.
    Inventors: Shih-Han Chen, Huabin Liao, Changlin Zhao
  • Patent number: 10430364
    Abstract: When a first interface board receives from an Ethernet switch chip a first Ethernet data packet, once a destination board of the data packet is determined as second interface board logical device of the first interface board encapsulates the data packet into a PCI-E packet that takes a PCI-E memory space address of a board memory in the second interface board as a destination address, so as to enable a PCI-E Endpoint to forward the first PCI-E packet to a forwarding board of a network device; when the first interface board obtains from a board memory a second PCI-E packet coming from a third interface board, logical device of the first interface board parses out a Ethernet data packet from the second PCI-E packet, and transmits the data packet to the Ethernet switch chip, the third interface board and second interface board being the same or not same.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 1, 2019
    Assignee: New H3C Technologies Co., Ltd.
    Inventors: Zhiyu Zhao, Changlin Mu, Yanfeng Zuo
  • Patent number: 10419355
    Abstract: In an example, a logic apparatus of an interface board in a network device may generate an Ethernet flow control packet including sending completion information according to Ethernet data packets sent from a sending buffering queue maintained in the interface board. The logic apparatus of the interface board may transmit the Ethernet flow control packet including sending completion information to an Ethernet data channel by taking priority over Ethernet data packets in a receiving buffering queue in an ingress direction. The sending completion information is used by a CPU of a mainboard to maintain a state of the sending buffering queue.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 17, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Zhiyu Zhao, Ze Zhang, Changlin Mu
  • Patent number: 10385189
    Abstract: The present invention provides a graphene composite powder form material that is suitable for industrialized application. The graphene composite powder form material is composited by graphene materials and a high-molecular compound. The high-molecular compound is uniformly coated on surfaces of the graphene material. Any adjacent graphene materials are separated by the high-molecular compound. An apparent density of the graphene composite powder form material is larger than or equal to 0.02 g/cm3. Under an external pressure, the graphene materials in the graphene composite powder form material do not re-stack, and can be easily restored to original form, which benefit the storage and transportation. Besides, the graphene composite powder form material has a good compatibility in other material systems, which greatly broadens the application fields in the downstream products and successfully solves the problem in industrial application.
    Type: Grant
    Filed: January 16, 2016
    Date of Patent: August 20, 2019
    Assignees: NINGBO MORSH TECHNOLOGY CO., LTD., NINGBO INSTITUTE OF MATERIALS TECHNOLOGY AND ENGINEERING, CHINESE ACADEMY OF SCIENCES
    Inventors: Zhaoping Liu, Xufeng Zhou, Changlin Tang, Zhihong Qing, Yongsheng Zhao