Abstract: Disclosed is a liquid-phase alloy catalyst, method of manufacturing same and two-dimensional chalcogenide thin film comprising thermodynamically induced grain boundary in monolayer crystal using same. In detail, a liquid-phase alloy catalyst for synthesizing a two-dimensional chalcogenide thin film, the liquid-phase alloy catalyst comprising an alloy including an alkali metal, a transition metal and an oxygen atom. The present disclosure has the effect of stably providing a uniform chemical environment through an independent liquid alloy catalyst in a chemically non-uniform synthetic environment.

Abstract: Disclosed is an electronic device. The electronic device of the present invention comprises: a communication unit; a storage unit for storing a uniform resource locator (URL) designated by an external electronic device and information on specific content provided in the designated URL; and a processor which, when a request for a connection to a designated URL is received from an external electronic device through the communication unit, identifies whether specific content can be provided in the designated URL, and in a case where the specific content cannot be provided, obtains information on another URL that provides content related to the specific content by using stored information, and transmits the obtained information on the another URL to the external electronic device through the communication unit.

Abstract: Disclosed is an electronic device. The electronic device of the present invention comprises: a communication unit; a storage unit for storing a uniform resource locator (URL) designated by an external electronic device and information on specific content provided in the designated URL; and a processor which, when a request for a connection to a designated URL is received from an external electronic device through the communication unit, identifies whether specific content can be provided in the designated URL, and in a case where the specific content cannot be provided, obtains information on another URL that provides content related to the specific content by using stored information, and transmits the obtained information on the another URL to the external electronic device through the communication unit.

Abstract: A method of forming a coating layer, including preparing hollow inorganic particles, each hollow inorganic particle including a shell surrounding a hollow core; preparing inorganic coating particles of a solid structure; forming a mixture of the hollow inorganic particles and the inorganic coating particles; and spraying the mixture on a surface of a base by a plasma spray coating process.

Abstract: A method of forming a coating layer, including preparing hollow inorganic particles, each hollow inorganic particle including a shell surrounding a hollow core; preparing inorganic coating particles of a solid structure; forming a mixture of the hollow inorganic particles and the inorganic coating particles; and spraying the mixture on a surface of a base by a plasma spray coating process.

Abstract: A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.

Abstract: A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.

Abstract: A method for transmitting Ethernet data in a Digital Unit (DU) that processes a baseband and interfaces with at least two Radio Frequency (RF) Units (RUs) is provided. The method includes setting location information of two or more Ethernet channels in a first subchannel of a radio frame, allocating the two or more Ethernet channels in second subchannels of the radio frame, using the location information, and transmitting the radio frame to the at least two RUs.

Abstract: A method for transmitting Ethernet data in a Digital Unit (DU) that processes a baseband and interfaces with at least two Radio Frequency (RF) Units (RUs) is provided. The method includes setting location information of two or more Ethernet channels in a first subchannel of a radio frame, allocating the two or more Ethernet channels in second subchannels of the radio frame, using the location information, and transmitting the radio frame to the at least two RUs.

Abstract: The present invention relates to an antioxidant composition and a method of preparation thereof. In detail, the present invention relates to an antioxidant composition containing procyanidin B3 obtained from Rosa multiflora, and a preparation method for the antioxidant composition, comprising extraction of the underground part of Rosa multiflora with an organic solvent, followed by fractionation and purification of the extract by chromatography. The antioxidant composition of the present invention can be effectively used in treatment or prevention of various diseases due to oxidation by reactive oxygen species, maintenance of quality of food, and prevention of skin damages due to oxidation.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.

Abstract: An end point detection window prevents process failures in a plasma etching device. The end point detection window has a body of aluminum or an aluminum alloy through which a hole extends to provide a path along which light generated during the etching process can pass from the process chamber, and a capping section coupled to a light outlet of the body. The capping section is of quartz for allowing the light passing through the hole in the body to be transmitted out of the process chamber.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: The present invention relates to an antioxidant composition and a method of preparation thereof. In detail, the present invention relates to an antioxidant composition containing procyanidin B3 obtained from Rosa multiflora, and a preparation method for the antioxidant composition, comprising extraction of the underground part of Rosa multiflora with an organic solvent, followed by fractionation and purification of the extract by chromatography. The antioxidant composition of the present invention can be effectively used in treatment or prevention of various diseases due to oxidation by reactive oxygen species, maintenance of quality of food, and prevention of skin damages due to oxidation.

Abstract: An end point detection window prevents process failures in a plasma etching device. The end point detection window has a body of aluminum or an aluminum alloy through which a hole extends to provide a path along which light generated during the etching process can pass from the process chamber, and a capping section coupled to a light outlet of the body. The capping section is of quartz for allowing the light passing through the hole in the body to be transmitted out of the process chamber.

Abstract: A chuck assembly of an etching apparatus capable of improving an etching rate at an edge portion of a wafer, thereby preventing byproducts from being formed along the edge portion of the wafer is disclosed. The chuck assembly comprises a chuck body comprising a stepped portion at an edge side portion of the chuck body for supporting a central portion of a wafer; an edge ring, received in the stepped portion of the chuck body, for supporting an edge portion of the wafer, wherein the edge ring has less resistance than the resistance of the wafer; and an insulating ring provided at a surrounding portion of the chuck body, for supporting a bottom portion of the edge ring, the bottom portion of the edge ring being extended toward outside of the chuck body.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode.