Patents by Inventor Changyok Park
Changyok Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128023Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventor: Changyok Park
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Patent number: 11923150Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: GrantFiled: May 27, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventor: Changyok Park
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Publication number: 20230207455Abstract: Integrated circuit structures having anti-fuse structures, and methods of fabricating integrated circuit structures having anti-fuse structures, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A first gate structure is over the first vertical stack of horizontal nanowires, the first gate structure including a first gate dielectric and a first gate electrode completely surrounding a channel region of each nanowire of the first vertical stack of horizontal nanowires. The integrated circuit structure also includes a second vertical stack of horizontal nanowires. A second gate structure is over the second vertical stack of horizontal nanowires, the second gate structure including a second gate dielectric and a second gate electrode only partially surrounding a channel region of each nanowire of the second vertical stack of horizontal nanowires.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventor: Changyok PARK
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Publication number: 20230207465Abstract: Integrated circuit structures having a buried power rail are described. In an example, an integrated circuit structure includes a device layer including a drain structure having an uppermost surface. A buried power rail is within the device layer and is neighboring the drain structure, the buried power rail having an uppermost surface below the uppermost surface of the drain structure. A top-side power rail is vertically over the buried power rail, the top-side power rail having a bottommost surface above the uppermost surface of the drain structure. A conductive structure is directly coupling the top-side power rail to the buried power rail.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Andy Chih-Hung WEI, Changyok PARK
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Publication number: 20230197767Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a decoupling capacitor within a multilayer die using hybrid bonding. Dummy bond pads may be used to form plates for the capacitor and a high-k dielectric material may be deposited between the plates prior to hybrid bonding. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventor: Changyok PARK
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Publication number: 20220416017Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to well biasing using a buried power rail (BPR) within a circuit structure. Embodiments include using a silicide material between the BPR and a well, where the silicide material provides ohmic contact between the BPR and the well. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Changyok PARK, Andy Chih-Hung WEI
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Publication number: 20220415572Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to forming capacitors using lines in a bond pad layer within hybrid bonding techniques of two separate dies and then coupling those dies. In embodiments, these techniques may involve using dummy bond pads, where the width of these dummy bond pads are smaller than that of active bond pads, to create a pattern to serve as a capacitor structure. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventor: Changyok PARK
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Publication number: 20220254872Abstract: Disclosed herein are IC structures with decoupling capacitors based on dummy TSV plates provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example decoupling capacitor includes first and second capacitor plates and a capacitor insulator between them. Each capacitor plate is a different blind, plate-like opening in the support structure, the openings at least partially filled with one or more conductive materials. The capacitor plate openings are referred to herein as “dummy TSV plates” because they may be fabricated while providing regular TSV openings in the support structure. Such decoupling capacitors may be better suited for high-speed microprocessor applications than conventional off-chip decoupling capacitors and may advantageously allow integrating on-chip decoupling capacitors with an ample amount of capacitive decoupling, limited or no additional processing steps on top of regular TSV processing, and in areas that may not have been used otherwise.Type: ApplicationFiled: February 9, 2021Publication date: August 11, 2022Applicant: Intel CorporationInventor: Changyok Park
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Publication number: 20220190129Abstract: Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.Type: ApplicationFiled: December 16, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Andy Chih-Hung Wei, Changyok Park, Guillaume Bouche, Hyuk Ju Ryu, Charles Henry Wallace, Mohit K. Haran
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Publication number: 20220157722Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.Type: ApplicationFiled: November 17, 2020Publication date: May 19, 2022Applicant: Intel CorporationInventors: Guillaume Bouche, Andy Chih-Hung Wei, Changyok Park
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Patent number: 11222869Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.Type: GrantFiled: January 14, 2019Date of Patent: January 11, 2022Assignee: ATI Technologies ULCInventor: Changyok Park
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Publication number: 20210375551Abstract: Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the second side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Applicant: Intel CorporationInventor: Changyok Park
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Patent number: 10396070Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.Type: GrantFiled: February 22, 2018Date of Patent: August 27, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Shom Surendran Ponoth, Changyok Park, Akira Ito
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Publication number: 20190148345Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Applicant: ATI Technologies ULCInventor: Changyok Park
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Patent number: 10181454Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.Type: GrantFiled: March 3, 2010Date of Patent: January 15, 2019Assignee: ATI Technologies ULCInventor: Changyok Park
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Publication number: 20180182753Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.Type: ApplicationFiled: February 22, 2018Publication date: June 28, 2018Inventors: Shom Surendran PONOTH, Changyok PARK, Akira ITO
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Patent number: 9941271Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.Type: GrantFiled: October 31, 2013Date of Patent: April 10, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Shom Surendran Ponoth, Changyok Park, Akira Ito
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Publication number: 20160233212Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.Type: ApplicationFiled: April 13, 2016Publication date: August 11, 2016Inventors: Shom Surendran PONOTH, Changyok PARK, Guang-Jye SHIAU, Akira ITO
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Patent number: 9337188Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.Type: GrantFiled: November 5, 2013Date of Patent: May 10, 2016Assignee: Broadcom CorporationInventors: Shom Surendran Ponoth, Changyok Park, Guang-Jye Shiau, Akira Ito
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Publication number: 20160064417Abstract: A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.Type: ApplicationFiled: November 5, 2015Publication date: March 3, 2016Inventors: Shom Surendran PONOTH, Changyok PARK