Abstract: An interconnect structure that in one embodiment can include a first metal line level having a first metal line, a second metal line level having a second metal line, and a via line level present between the first and second metal line levels. The via line level includes a via interlevel dielectric surrounding a via stack. The via stack may include an interface metal portion that is in contact with the first metal line, a via intralevel dielectric on the interface metal portion, and a cap metal portion in contact with the second metal line and extending through the via intralevel dielectric into contact with the interface metal portion. In some embodiments, the length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack.

Abstract: An approach provides a semiconductor structure with one or more rectangular or square-shaped contact vias in a semiconductor material. The semiconductor device includes one of the first element of the semiconductor device element under the square-shaped contact via or the second element of the semiconductor device element above the square-shaped contact via. The semiconductor structure includes the square-shaped via in the semiconductor material that has straight edges that are parallel to one or more of the (110) crystal planes of the semiconductor material and the square-shaped contact vias has corners pointing in a direction orthogonal to one or more of the (100) crystal planes of the semiconductor material. The square-shaped contact via provides a larger contact area that a conventional round-shaped contact via with a diameter matching the width of the square-shaped contact via.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor, a second transistor, and a third transistor separated by their respective source/drain regions; and a diffusion break between the second transistor and the third transistor, wherein a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor is more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor. A method of manufacturing the semiconductor structure is also provided.

Abstract: A memory structure including a magnetic tunnel junction (MTJ) structure and a top electrode that are both formed without utilizing ion beam etching is provided. The MTJ structure, which includes a lower magnetic stack, a tunnel barrier layer and an upper magnetic stack, is pyramidal shaped, and end portions of the lower magnetic stack of the MTJ structure are devoid of the tunnel barrier layer and the upper magnetic stack.

Abstract: A substrative patterning process is provided that forms an interconnect structure including a connector tab located between two adjacent electrically conductive line structures. The connector tab and the two adjacent electrically conductive line structures are of unitary construction and are located in a same metallization level.

Abstract: A method includes providing a semiconductor structure comprising an insulating layer, forming sacrificial mandrel features on top of the insulating layer, and forming a spacer layer by depositing spacer material conformally around the sacrificial mandrel features. The method includes forming a non-mandrel cut region between a first sacrificial mandrel feature and a second sacrificial mandrel feature of the sacrificial mandrel features, forming a first layer region in the non-mandrel cut region, and forming a mandrel cut region by removing a third sacrificial mandrel feature of the sacrificial mandrel features. The method further includes forming a second placeholder layer in the removed portion of the third sacrificial mandrel feature, performing a mandrel pull-back process to remove the first sacrificial mandrel feature and the second sacrificial mandrel feature, and adjusting a thickness of sidewalls of the spacer layer exposed by the mandrel pull-back process.

Abstract: A semiconductor device is provided including frontside interconnects (i.e., metal wires) used mainly as power supplies and backside interconnects (i.e., metal wires) used mainly as signal wiring. The semiconductor device includes a frontside back-end-of-the-line (BEOL) structure including frontside metal wires located in the frontside of the device, and a backside BEOL interconnect structure including backside metal wires located in a backside of the device. At least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires.

Abstract: A semiconductor structure having a high cell density is provided in which a frontside dynamic access memory (DRAM) is located on a frontside of a semiconductor substrate, and a backside DRAM is located on a backside of the semiconductor substrate. Peripheral transistors can be located on the frontside of the semiconductor substrate and at a same level as frontside transistors of the frontside DRAM.

Abstract: A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.

Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and a second nano device that includes a plurality of second transistors. The first nano device and the second nano device are parallel to each other. A double diffusion break that extends across the first nano device and the second nano device. A back-end-of-the-line (BEOL) layer located on a frontside of the first nano device and the second nano device. A backside interconnect located on a backside of the first nano device and the second nano device and the BEOL layer is connected to the backside interconnect through the double diffusion break.

Abstract: A method of making a semiconductor component includes forming an interconnect in a dielectric layer such that an uppermost surface of the interconnect is substantially coplanar with an uppermost surface of the dielectric layer. The method further includes recessing the dielectric layer such that the uppermost surface of the dielectric layer is lower than the uppermost surface of the interconnect. The method further includes forming spacers in direct contact with the uppermost surface of the recessed dielectric layer such that the spacers are in direct contact with the interconnect. The method further includes recessing the interconnect such that the uppermost surface of the interconnect remains above the uppermost surface of the recessed dielectric layer and is lower than an uppermost surface of the spacers.

Abstract: Methods of filling a gap in a semiconductor structure are presented. A titanium nitride and sacrificial silicon nitride spacer is deposited onto a line pattern comprising a trench between two lines of the line pattern. The titanium nitride and sacrificial silicon nitride spacer is etched to leave titanium nitride and sacrificial silicon nitride spacer covering sides of the two lines within the trench. An organic planarization layer is applied over the line pattern and the titanium nitride and sacrificial silicon nitride spacer. A pillar cut is cut through the organic planarization layer and into the trench to form a gap within the trench. The gap is filled with silicon oxide.

Abstract: A SRAM is provided that includes a first pull-up transistor having a first channel length, and a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length. The structure further includes a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety thereof, and a second backside contact structure having a vertical portion and a base portion. The vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first interlayer dielectric (ILD) layer and a second ILD layer formed above the first ILD layer. The semiconductor interconnect structure further includes two adjacent metal lines formed within the second ILD layer and an air gap formed within a portion of the second ILD layer located between the two adjacent metal lines. The first ILD layer directly contacts the second ILD layer in a first region located below the air gap, and the first ILD layer and the second ILD layer are separated by an etch stop layer in a second region located outside of the first region.

Abstract: Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside. A backside contact is coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer.

Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

Abstract: Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

Abstract: A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source/drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source/drain regions. The backside isolation region has a reverse tapered profile.

Abstract: A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.

Abstract: A semiconductor device includes a first gate upon a semiconductor substrate and a second gate upon the semiconductor substrate in line with the first gate. A gate cut dielectric is between the first gate and the second gate. A first gate cap is upon a top surface of the first gate and a second gate cap is upon a top surface of the second gate. A gate cut multilayer structure is between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first substantially vertical spacer and a second substantially vertical spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate.