Patents by Inventor Chanro Park

Chanro Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013322
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 14, 2021
    Inventors: Ruilong Xie, Kangguo Cheng, Chanro Park, Juntao Li
  • Patent number: 10886378
    Abstract: A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 5, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Julien Frougier, Chanro Park, Kangguo Cheng
  • Patent number: 10879073
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Publication number: 20200402976
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Application
    Filed: July 28, 2020
    Publication date: December 24, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Publication number: 20200395238
    Abstract: Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Kangguo Cheng, CHANRO PARK, JUNTAO LI, Ruilong Xie
  • Publication number: 20200386685
    Abstract: An apparatus includes a substrate having a base and a plurality of pillars extending from the base where the pillars are configured to define a nano-array, a dielectric disposed on the base, and a plasmonic coating disposed on a surface of the dielectric and on one or more of the pillars.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Publication number: 20200388694
    Abstract: A semiconductor device includes a gate having a gate spacer formed on a semiconductor substrate and a source or drain (S/D) formed on the substrate a distance away from the gate. A S/D contact including a contact spacer is formed on an upper surface of the S/D. A dielectric layer is interposed between the gate spacer and the contact spacer; and an airgap is in the dielectric layer.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Publication number: 20200381306
    Abstract: Embodiments of the present invention are directed to a gate cap last process for forming a self-aligned contact. This gate cap last process allows for a thin SAC cap, as the SAC cap only needs to prevent a short between the metallization contact and the gate. In a non-limiting embodiment of the invention, a gate is formed over a channel region of a fin. The gate can include a gate spacer. A sacrificial contact is formed on a top surface of a source or drain (S/D) region of a substrate. The sacrificial contact is positioned directly adjacent to a sidewall of the gate spacer. An exposed surface of the gate is recessed to form a recessed gate surface and a self-aligned contact (SAC) cap is formed on the recessed gate surface. The sacrificial contact is replaced with a S/D contact.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Choonghyun Lee
  • Publication number: 20200373165
    Abstract: A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Juntao Li
  • Publication number: 20200365607
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 19, 2020
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Patent number: 10840148
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Ruilong Xie, Chanro Park
  • Publication number: 20200357896
    Abstract: A method for manufacturing a semiconductor device includes patterning a plurality of semiconductor fins on a semiconductor substrate, and replacing at least two of the plurality of semiconductor fins with a plurality of dummy fins including a dielectric material. A gate structure is formed on and around the plurality of semiconductor fins and the plurality of dummy fins, and a source/drain contact is formed adjacent the gate structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Kangguo Cheng, Ruilong Xie, Juntao Li, Chanro Park
  • Publication number: 20200357911
    Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • Patent number: 10832944
    Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Chanro Park, Ruilong Xie, Andre P. Labonte
  • Patent number: 10832947
    Abstract: A method is presented for forming fully aligned vias without recessing a plurality of conductive lines. The method includes forming the plurality of conductive lines within an interlayer dielectric (ILD), growing first dielectric regions in direct contact with the plurality of conductive lines, forming a capping layer over the first dielectric regions, depositing an ultra-low-k (ULK) layer over and in direct contact with the capping layer, forming a via over a conductive line of the plurality of conductive lines, and removing an exposed portion of the capping layer and an exposed first dielectric region in direct contact with the conductive line to reveal the conductive line.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 10832961
    Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Ruilong Xie, Veeraraghavan S. Basker, Andre P. Labonte, Chanro Park
  • Patent number: 10832964
    Abstract: A semiconductor structure is disclosed including a semiconductor substrate having two or more fins. The semiconductor structure includes a recessed gate structure having opposing sidewalls located over one of the fins. The semiconductor structure includes a gate spacer disposed on the opposing sidewalls of the recessed gate structure. The semiconductor structure includes a source/drain region disposed between adjacent gate spacers. The semiconductor structure includes a first conductive material disposed on the source/drain region and an interlevel dielectric layer disposed on a top surface of the semiconductor structure defining an opening therein to an exposed top surface of the first conductive material. A width of an upper portion of the opening is greater than the width of the lower portion of the opening. The lower portion of opening is aligned with the first conductive material. The semiconductor structure includes a second conductive material disposed in the opening.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporatior
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Chanro Park, Nicolas Loubet
  • Patent number: 10833165
    Abstract: In a semiconductor device being fabricated, a gate structure, a first source/drain (S/D) structure, and a second S/D structure are formed. A first spacer of a first dielectric material is formed between the gate structure and the first S/D structure. A second spacer is formed between the gate structure and the second S/D structure, such that a first gap is created within a second dielectric material of the second spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Son Nguyen, Chanro Park
  • Publication number: 20200350313
    Abstract: A semiconductor device includes a first transistor including a first vertical fin arranged between first bottom source or drain (S/D) region and first top S/D region, and a first recessed gate stack arranged on a sidewall of the first vertical fin. A second transistor includes second vertical fin arranged between a second bottom S/D region and second top S/D region, and a second recessed gate stack arranged on a sidewall of the second vertical fin. A first spacer contacts the sidewall of the first vertical fin and on the first recessed gate stack or the second recessed gate stack. A second spacer contacts the first spacer of the first transistor or the second transistor. The second spacer is on a sidewall of the top S/D region of the first transistor or second transistor. The inner spacer and the outer spacer include different materials.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Inventors: RUILONG XIE, MUTHUMANICKAM SANKARAPANDIAN, CHANRO PARK, KANGGUO CHENG
  • Publication number: 20200335401
    Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Inventors: Su Chen Fan, Ruilong Xie, Veeraraghavan S. Basker, Andre P. Labonte, Chanro Park