Abstract: A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

Abstract: A contact structure having reduced middle-of-the-line (MOL) resistance is provided that includes a source/drain contact which includes a liner and a via contact that is liner-less. The via contact includes a first via portion having a first critical dimension and a second via portion having a second critical dimension that is greater than the first critical dimension. The second critical dimension provides a maximized via contact bottom critical dimension over the source/drain contact, while the first critical dimension provides sufficient area between the first via portion of the via contact and a neighboring electrically conductive structure thus avoiding any shorts between those two elements.

Abstract: A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.

Abstract: A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Abstract: Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.

Abstract: A semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. The capacitor structure includes first and second electrode layers separated by a dielectric layer. A top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. A spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.

Abstract: A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

Abstract: An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.

Abstract: Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

Abstract: A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.

Abstract: A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Abstract: A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.

Abstract: A lower set of semiconductor channel layers, an upper set of semiconductor channel layers, a lower dielectric layer adjacent to the lower set of semiconductor channel layers, the lower dielectric layer includes a first polarity stress on the lower set of semiconductor channel layers, and an upper dielectric layer adjacent to the upper set of semiconductor channel layers, the lower dielectric layer includes a second polarity stress on the upper set of semiconductor channel layers with opposite polarity stress of the first polarity stress. Forming a lower stack of nanosheet layers and an upper stack of nanosheet layers, forming a lower dielectric layer adjacent to the lower stack of nanosheet layers, the lower dielectric layer includes a first polarity stress, and forming an upper dielectric layer adjacent to the upper stack of nanosheet layers, the upper dielectric layer includes a second polarity stress with opposite polarity.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

Abstract: A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Abstract: A CMOS apparatus includes a semiconductor substrate that has a frontside and a backside opposite the frontside; a source/drain structure, which is disposed at the frontside of the substrate and has a backside that is adjacent to the substrate and a frontside that is opposite the backside of the source/drain structure; a backside interconnect layer, which is disposed at the backside of the substrate; a backside contact, which penetrates the substrate and electrically connects the source/drain structure to the backside interconnect layer; and a sigma-profiled dielectric structure that insulates first and second sides of the backside contact from the substrate.

Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.

Abstract: A semiconductor device including a substrate having a dense array region and an isolation region. The semiconductor device includes plurality of first fin structures of stacked nanosheets is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first nanosheet height as measured from an upper surface of the substrate in the dense array region. The semiconductor device further includes at least one second fin structure of stacked nanosheets is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one fin structure having a second nano sheet height that is measured from the upper surface of the substrate in the isolation region that is the same as the first nanosheet height.