Patents by Inventor Chao-Cheng Chen
Chao-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12364003Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: GrantFiled: November 24, 2023Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
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Publication number: 20250224736Abstract: A boundary defining method implemented by a boundary defining system comprises: (A) obtaining a piece of positioning data that includes a path record and a signal status record, the path record indicating a circling path defining a circled area, the signal status record indicating one or more risky path sections in the circling path that meet a poor signal condition; (B) based on each risky path section indicated by the signal status record, determining an alternative path section corresponding to the risky path section and located within the circled area; and (C) based on at least the alternative path section(s), generating and outputting a piece of operating range data indicating an operating boundary, the operating boundary defining an operating area suitable for automatic movement of an autonomous mobile operation equipment, and that does not include the risky path section(s).Type: ApplicationFiled: January 8, 2025Publication date: July 10, 2025Inventors: Chien-Tung CHEN, Chung-Hou WU, Chao-Cheng CHEN, Dien-Lin TSAI
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Publication number: 20250221027Abstract: A device includes a channel structure, a gate structure, a first source/drain epitaxial structure, and a second source/drain epitaxial structure. The channel layer is over a substrate and extends in a first direction. The gate structure covers the channel structure and extends in a second direction different from the first direction. The first source/drain structure and the second source/drain structure are on opposite sides of the channel structure. A void is contained in between the first source/drain structure and the substrate.Type: ApplicationFiled: March 19, 2025Publication date: July 3, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Pi TSENG, De-Fang CHEN, Chao-Cheng CHEN
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Patent number: 12346124Abstract: A method for controlling a plurality of mobile robots is to be implemented by a server that communicates with the plurality of mobile robots and a communication device. The server stores a predetermined working route related to a target area. The method includes steps of: receiving a working instruction from the communication device, the working instruction including area information related to the target area and an input quantity of mobile robots; in response to receipt of the working instruction, dividing the predetermined working route into a plurality of sub-routes, wherein a quantity of the sub-routes equals the input quantity of mobile robots; and sending the sub-routes respectively to a plurality of selected robots that are selected from among the plurality of mobile robots to make the selected robots cooperatively implement a task on the target area by moving along the sub-routes, respectively.Type: GrantFiled: July 31, 2023Date of Patent: July 1, 2025Assignee: URSROBOT AI INC.Inventors: Chien-Tung Chen, Chung-Hou Wu, Chao-Cheng Chen, Wen-Wei Chiang, Yi-Jin Lin
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Publication number: 20250203902Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.Type: ApplicationFiled: February 28, 2025Publication date: June 19, 2025Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 12322057Abstract: In many applications, the assessment of the internal structures of tubular structures (such as in medical imaging, blood vessels, bronchi, and colon) has become a topic of high interest. Many 3D visualization techniques, such as “fly-through” and curved planar reformation (CPR), have been used for visualization of the lumens for medical applications. However, all the existing visualization techniques generate highly distorted images of real objects. This invention provides direct manipulation based on the centerline of the object and visualization of the 3D internal structures of a tubular object without any noticeable distortion. For the first time ever, the lumens of a human colon is visualized as it is in reality. In many medical applications, this can be used for diagnosis, planning of surgery or stent placements, etc. and consequently improves the quality of healthcare significantly. The same technique can be used in many other applications.Type: GrantFiled: February 17, 2022Date of Patent: June 3, 2025Inventors: Chao-Cheng Chen, Chao-Yu Chen
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Publication number: 20250176251Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: January 27, 2025Publication date: May 29, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Publication number: 20250169150Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
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Patent number: 12300742Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal.Type: GrantFiled: January 10, 2024Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 12294023Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.Type: GrantFiled: August 9, 2022Date of Patent: May 6, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 12288812Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.Type: GrantFiled: June 2, 2022Date of Patent: April 29, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Ke-Chia Tseng, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 12283596Abstract: A device includes a substrate, a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer and are connected to the channel layer. The bottom dielectric structure is between the first source/drain epitaxial structure and the substrate. A maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view.Type: GrantFiled: July 7, 2023Date of Patent: April 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Pi Tseng, De-Fang Chen, Chao-Cheng Chen
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Publication number: 20250120167Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Publication number: 20250120151Abstract: A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: KUEI-YU KAO, Shih-Yao LIN, Chen-Ping Chen, Chih-Han Lin, MING-CHING CHANG, CHAO-CHENG CHEN
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Patent number: 12271207Abstract: A method for controlling a plurality of autonomous robots for performing environment maintenance operations includes: generating a setup command that indicates a selected location, a plurality of selected robots, an available time slot, and a distribution mode signal that indicates whether the selected robots are to be controlled based on the available time slot or an inputted priority section; and generating a plurality of sub-routes based on different parameters, depending on the distribution mode signal. The sub-routes are generated to be connected into an unbroken trail. Then, the sub-routes are transmitted to the selected robots, respectively, so as to control each of the selected robots to move along the respective one of the sub-routes.Type: GrantFiled: July 31, 2023Date of Patent: April 8, 2025Assignee: URSrobot AI Inc.Inventors: Chien-Tung Chen, Chung-Hou Wu, Chao-Cheng Chen, Wen-Wei Chiang, Yi-Jin Lin
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Patent number: 12243748Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.Type: GrantFiled: July 20, 2022Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 12243924Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.Type: GrantFiled: March 13, 2023Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
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Patent number: 12230545Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: GrantFiled: November 30, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Patent number: 12220425Abstract: Provided is a method of preventing or treating gastroesophageal reflux disease, including administering to an subject in need thereof a composition including a plurality of fibers formed of ?-1-4-glucan, wherein the fibers have a diameter between 15 nm and 35 nm and a mean length of between 1.5 ?m and 3.5 ?m.Type: GrantFiled: November 16, 2021Date of Patent: February 11, 2025Inventor: Chao-Cheng Chen
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Patent number: 12199151Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: GrantFiled: January 30, 2024Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen