Patents by Inventor Chao-Cheng Chen

Chao-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10473613
    Abstract: Light-addressable potentiometric sensing units are provided. A light-addressable potentiometric sensing unit comprises a conductive substrate, a metal oxide semiconductor layer, and a sensing layer. The metal oxide semiconductor layer is made of indium gallium zinc oxide, indium gallium oxide, indium zinc oxide, indium oxide co-doped with tin and zinc, tin oxide, or zinc oxide. The wide-band gap characteristic of the metal oxide semiconductor layer enables the light-addressable potentiometric sensing unit to resist the interference from visible light. The light-addressable potentiometric sensing unit therefore exhibits a more stable performance.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: November 12, 2019
    Assignee: CHANG GUNG UNIVERSITY
    Inventors: Chao-Sung Lai, Chia-Ming Yang, Chun-Hui Chen, Tsung-Cheng Chen
  • Publication number: 20190322762
    Abstract: An antibody, or an antigen-binding fragment there, binding human ENO1 (GenBank: AAH506421.1) is provided. Methods for treating an ENO1 protein-related disease or disorder, inhibiting cancer invasion and diagnosis of cancer are also provided.
    Type: Application
    Filed: March 19, 2018
    Publication date: October 24, 2019
    Applicants: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: SHIH-CHONG TSAI, TA-TUNG YUAN, SHIH-CHI TSENG, JIANN-SHIUN LAI, CHIA-CHENG WU, PO-YIN LIN, YA-WEI TSAI, CHAO-YANG HUANG, YING-YUNG LOK, CHUNG-HSIUN WU, HSIEN-YU TSAI, NENG-YAO SHIH, KO-JIUNN LIU, LI-TZONG CHEN
  • Publication number: 20190309092
    Abstract: The present invention provides a modified antigen-binding Fab fragment. An antigen-binding molecule comprising the antigen-binding Fab fragment and a composition comprising the molecule are also provided.
    Type: Application
    Filed: July 20, 2017
    Publication date: October 10, 2019
    Applicant: Development Center for Biotechnology
    Inventors: Chih-Yung HU, Chao-Yang HUANG, Yu-Jung CHEN, Chia-Cheng WU, Chien-Tsun KUAN, Chia-Hsiang LO, Hsien-Yu TSAI
  • Publication number: 20190312138
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20190288084
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ricky WANG, Chao-Cheng CHEN, Jr-Jung LIN, Chi-Wei YANG
  • Patent number: 10418460
    Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
  • Publication number: 20190227601
    Abstract: A lifting device is applied to an input assembly, and includes: a base, a supporting base, and a connecting rod mechanism, where the base bears the input assembly and includes a lower protruding portion; the supporting base is movably disposed corresponding to the base and includes a base portion and a notch, and the notch is disposed corresponding to the lower protruding portion; the connecting rod mechanism includes an output rod and an input rod, where the output rod is connected to the supporting base; the input rod is linked with the output rod, and drives the output rod to move, so that the supporting base moves relative to the base, and when movement of the supporting base makes the lower protruding portion move from the notch to the base portion, the base ascends by a height.
    Type: Application
    Filed: November 21, 2018
    Publication date: July 25, 2019
    Inventors: Yen-Chih KUO, Hung-Cheng LEE, Tzu-Ming YANG, Cheng-Shi JIANG, Chao-Kai HUANG, Jeng-Hong CHIU, Chih-Ming CHEN, Chih-Liang CHIANG
  • Patent number: 10349542
    Abstract: The present disclosure provides a latch assembly for securing an electronic component within a computing device. The latch assembly includes a latch, a base, and a cover. The latch includes a first structural member with a first plurality of pins; a second structural member with a second plurality of pins; at least one linking element that connects the first structural member with the second structural member; and a first securing element located at the first structural member. The base includes a receiving space for receiving the latch; a first plurality of slots configured to receive the first plurality of pins; a second plurality of slots configured to receive the second plurality of pins; a plurality of protruding elements; and a second securing element corresponding with the first securing element. The cover is secured to the base at the plurality of protruding elements.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 9, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Hsiang Lee, Kun-Pei Liu, Tsung-Cheng Lin
  • Publication number: 20190205357
    Abstract: A method for browsing virtual reality (VR) webpage content is provided. The browsing method includes: identifying a device information of a VR helmet by a native application; sending out a notification message by a first browser when it is detected that a VR webpage is browsed; retrieving a webpage information corresponding to the VR webpage and providing the webpage information to the native application by an extension component of the first browser in response to the notification message; determining, by the native application, whether the first browser supports the VR helmet to display a VR content of the VR webpage according to the device information; opening the VR webpage through a second browser, which supports the VR helmet to display the VR content, by the native application according to the webpage information when it is determined that the first browser does not support the VR helmet.
    Type: Application
    Filed: December 11, 2018
    Publication date: July 4, 2019
    Applicant: Acer Incorporated
    Inventors: Shih-Hao LIN, Chao-Kuang YANG, Wen-Cheng HSU, Chih-Sheng CHEN, Siang-Jyun CHENG
  • Patent number: 10332991
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 10312158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Cheng Li, Chien-Hao Chen, Yung-Cheng Lu, Jr-Jung Lin, Chun-Hung Lee, Chao-Cheng Chen
  • Publication number: 20190122888
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 25, 2019
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Patent number: 10269937
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Patent number: 10269581
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
  • Publication number: 20190043763
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng LI, Chien-Hao CHEN, Yung-Cheng LU, Jr-Jung LIN, Chun-Hung LEE, Chao-Cheng CHEN
  • Patent number: 10170367
    Abstract: In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and the mandrels; depositing a dielectric layer over the mask layer and the mandrels, a first thickness of the dielectric layer along sidewalls of the mandrels being greater than a second thickness of the dielectric layer along the etch coating layer; removing horizontal portions of the dielectric layer; and patterning the mask layer using remaining vertical portions of the dielectric layer as an etching mask.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Hao-Ming Lien, Wei-Che Hsieh, Chun-Hung Lee
  • Patent number: 10157742
    Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Publication number: 20180350966
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20180323108
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10117956
    Abstract: The present invention is related to a radiolabeled active targeting pharmaceutical composition, including: a bioconjugate and a radionuclide, wherein the bioconjugate includes a biomolecule and a metal nanoparticle, wherein the biomolecule has an affinity for receptors on the surface of a cell membrane and is selected from the group consisting of a peptide and a protein. The present invention further provides a method for evaluating a thermal adjuvant therapy for tumors and a kit thereof. The above-mentioned pharmaceutical composition is applied to evaluate a tumor accumulation time, so as to establish the optimal policy for a radiofrequency- or laser-induced thermal adjuvant therapy for tumors.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 6, 2018
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Hsin-Ell Wang, Chien-Chung Hsia, Mao-Chi Weng, Kun-Liang Lin, Hao-Wen Kao, Chao-Cheng Chen, Kwan-Hwa Chi, Der-Chi Tien, Wuu-Jyh Lin