Abstract: A method and device for calibrating in-phase and quadrature-phase (IQ) mismatch. The device is used in a direct down-conversion circuit of a communication system. The device has a first mixer for mixing an RF signal with a first carrier signal, so as to generate an in-phase analog signal; a second mixer for mixing the RF signal with a second carrier signal, so as to generate a quadrature-phase analog signal; an operation unit for executing a Least Mean Square (LMS) algorithm and thereby generating a compensation signal according to the in-phase analog signal and the quadrature-phase analog signal; and a calibration unit for compensating the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal, so as to calibrate the IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal.

Abstract: The present invention discloses an apparatus for generating an output signal according to an input signal, including a signal generating circuit for generating a first and a second control signal according to the input signal; a first output stage has a first amplifying configuration for receiving the first control signal; and a second output stage has a second amplifying configuration for receiving the second control signal, wherein the first amplifying configuration is different from the second amplifying configuration.

Abstract: A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly.

Abstract: A common-mode feedback circuit is provided. An amplifier with a common-mode feedback circuit is compensated by adding a compensating unit so that the amplifier totally has two poles and one zero in its frequency response. Accordingly, the gain of the amplifier is not sacrificed, and both the stability and the phase margin of the circuit are improved.

Abstract: A low noise amplifier for operating in response to different gain modes is disclosed. The low noise amplifier includes a voltage adjusting circuit, which provides a first bias voltage at a first gain mode and provides a second bias voltage at a second gain mode, where the second bias voltage is different from the first bias voltage; and an amplifying circuit coupled to the voltage adjusting circuit, for providing a first transfer characteristic according to the first bias voltage during the first gain mode in order to amplify an input signal to generate an output signal, and for providing a second transfer characteristic according to the second bias voltage during the second gain mode in order to amplify the input signal to generate the output signal.

Abstract: An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.

Abstract: A bandgap voltage generating circuit includes a circuit coupled to a first node and a second node, driving the first and the second nodes to the same voltage level. A first impedance element is coupled to the first node and a second impedance element is coupled to the second node, wherein the impedance of the second impedance element is larger than the impedance of the first impedance element. A first transistor is coupled to the first impedance element, and a second transistor is coupled to the second impedance element and the first transistor. The bandgap generating circuit generates a bandgap voltage at the second node.

Abstract: A voltage regulating apparatus and method and voltage regulator thereof are presented. The apparatus includes a first regulator and a second regulator. The first regulator is used for receiving an input voltage and outputting a first voltage according to the input voltage. When the input voltage reaches a steady voltage value, the second regulator is turned on so as to receive the first voltage provided by the first regulator and output a second voltage according to the first voltage or the input voltage.

Abstract: A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.

Abstract: An audio processing system for used in a multi-channel audio chip includes a multiplexer, a digital-to-analog converter, a de-multiplexer, a controller and N sample-and-hold circuits. The multiplexer receives N digital signals and outputs the digital signals one by one in a time-division manner. The digital-to-analog converter receives the digital signals from the multiplexer and converts them into corresponding N analog signals. The de-multiplexer outputs the analog signals one by one in a time-division manner. The controller generates control signals to control the selection of the multiplexer and the de-multiplexer. The sample-and-hold circuits hold the analog signals for a predetermined period of time and then outputs the signals, respectively.

Abstract: A power managing apparatus is utilized to control a first supply voltage, a second supply voltage, and a substrate voltage of a digital circuit. The power managing apparatus includes a voltage generating device, for generating a first reference voltage and a second reference voltage; and a voltage switching device, coupled to the voltage generating device, for adjusting the first supply voltage, the second supply voltage, and the substrate voltage. When the digital circuit operates in a first operating mode, the voltage switching device outputs the second reference voltage to be the first supply voltage and the substrate voltage; and when the digital circuit operates in a second operating mode, the voltage switching device outputs the first reference voltage to be the first supply voltage, and outputs the second reference voltage to be the second supply voltage.

Abstract: A voltage converting circuit is able to convert an input voltage generated by a system to a voltage capable of being utilized by a chip, avoids the defects of conventional switching regulators and linear regulators, and achieves voltage regulation with extremely high power efficiency and without off-chip components. The voltage converting circuit is adapted in systems with a plurality of similar or identical circuits.

Abstract: An amplifier includes: a class AB input stage, receiving an input signal, for generating an inner signal according to the input signal; class AB output stage, includes: a biasing circuit, for providing a first voltage and a second voltage according to the inner signal; and an output stage, for generating an output signal according to the first voltage and the second voltage; wherein a voltage difference between the first voltage and the second voltage generated by the biasing circuit is corresponding to the input signal.

Abstract: The present invention provides a multi-phase layout structure and method. The layout structure comprises: a first layout layer; a second layout layer substantially parallel to the first layout layer; a plurality of traces, each transmitting a signal, and the plurality of signals having a phase difference between each other; wherein a horizontal coupling capacitance is provided between two neighboring traces configured on the same layer of the first layout layer and the second layout layer, a vertical coupling capacitance is provided between two neighboring traces configured on different layers of the first layout layer and the second layout layer, and the plurality of traces have substantially the same total coupling capacitance wherein the total coupling capacitance is defined by the horizontal coupling capacitance and the vertical coupling capacitance.

Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Abstract: This invention provides a charge pump circuit used in phase-locked loop (PLL) having the function of power management for portable application. According to different applications, power management adjusts the power consumption modes of this PLL that will also correspond to different jitter degree. There are three kinds of modes contained in the PLL: the first mode is normal mode having the larger power consumption and smaller jitter, second mode is low power mode having moderate power consumption and moderate jitter, and third mode is the traditional mode having the smaller power consumption and the larger jitter.

Abstract: A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

Abstract: A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Abstract: A mixing apparatus and related methods are provided. The mixing apparatus can filter out unwanted harmonic orders according to demands, to thereby increase circuit attribute performance. Regardless of the type of mixing circuit used for the mixing apparatus, the harmonic interfering phenomenon can be substantially improved.

Abstract: The present invention is to provide a latch-up resistant electrostatic discharge (ESD) protection circuit and method thereof, which comprises a clamping circuit being able to discharge when activated, a sustaining unit for directing electrostatic charge via said sustaining unit to said clamping circuit when activated and a sensing unit for activating said clamping circuit and said sustaining unit. When an ESD event, a signal noise or a power bounce is detected, said clamping circuit and said sensing unit is activated, said sustaining unit is activated to increase discharging ability of said clamping circuit, and then said sensing unit self resets after a period of time to deactivate said sustaining unit, thereby said clamping circuit is deactivated and a latch-up is prevented.