Abstract: An impedance apparatus for providing an equivalent impedance between a first node and a second node. The impedance apparatus includes a first impedance device having a first impedance value; a second impedance device having a second impedance value; a first switch element coupled to the first impedance device; a second switch element coupled to the second impedance device; and a controller coupled to the first switch element and the second switch element; wherein the first switch element is controlled by the controller to be periodically turned on and off, and the second switch element is controlled by the controller to be periodically turned on and off.

Abstract: A symmetric electrical connection system for balancing impedance between a first node and a third node and impedance between a second node and a fourth node. The system includes a first conducting wire, a third conducting wire, a fifth conducting wire, and a seventh conducting wire all installed in a first layer. The system further includes a second conducting wire, a fourth conducting wire, a sixth conducting wire, and an eighth conducting wire all installed in a second layer. The first conducting wire and the eighth conducting wire are crossed but electrically insulated. The second conducting wire and the third conducting wire are crossed but electrically insulated. The fourth conducting wire and the fifth conducting wire are crossed but electrically insulated. The sixth conducting wire and the seventh conducting wire are crossed but electrically insulated. In a preferred embodiment, the appearances and the materials of the conducting wires are essentially equivalent.

Abstract: The present invention discloses an impedance matching circuit with automatic adjustment and a method thereof. The impedance matching circuit comprises: a resistor, for receiving a reference voltage and generating a reference current; a detection unit, for detecting resistance variation and generating a plurality of comparison voltages according to said reference current; a comparison unit, for comparing said reference voltage with said comparison voltages, and generating a control signal; and a composite resistor unit, for receiving said control signal and generating a matched impedance. Therefore, a matched impedance value can be obtained within a designed range in despite of the manufacturing process and the operation environment.

Abstract: A method for detecting a phase difference between a first input signal and a second input signal is provided. The method contains: detecting the phase difference of the first and the second input signals to produce an output signal; generating a first voltage according to a first level of the output signal; generating a second voltage according to a second level of the output signal; and comparing the first voltage and the second voltage to produce the information regarding the phase difference between the first and the second input signals.

Abstract: A fast start-up low-voltage bandgap voltage reference circuit is disclosed. The bandgap voltage reference circuit includes: a first current generator, which is implemented by a self-bias unit and a current mirror for generating a first reference current with positive temperature coefficient; a second current generator, which is connected to a point with negative temperature coefficient in the first current generator to generate a second reference current with negative temperature coefficient; and a resistor for converting the first reference current and the second reference current into a low-voltage bandgap voltage independent of temperature. Because the bandgap voltage reference circuit of the invention uses the resistor to convert the first reference current and the second reference current into voltage, the circuit can provide low-voltage bandgap voltage.

Abstract: An apparatus for generating a phase delay is disclosed. The apparatus includes a buffer utilized for buffering an input signal and then outputting an output signal; a digital to analog converter (DAC) utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage; and a variable capacitor that has a capacitance value controlled by the control voltage. By controlling the variable capacitance value, the apparatus for generating a phase delay can adjust the phase delay between the input signal and the output signal.

Abstract: An ESD protection circuit installed among a plurality of reference nodes includes a clamping device coupled between two reference nodes among the plurality of reference nodes; a stack-coupling device coupled between the clamping device and one of the reference nodes; and at least a resistive device coupled between the stack-coupling device and another one of the reference nodes.

Abstract: A linear decibel-scale variable gain amplifier includes an amplifying stage for generating an output voltage according to a differential input voltage, and a gain-controlling stage for outputting a gain-controlling voltage to the amplifying stage according to a first controlling voltage and a second controlling voltage. A voltage gain of the linear decibel-scale variable gain amplifier is inversely proportional to a simple exponential function, and the value of the simple exponential function is determined by the difference between the first controlling voltage and the second controlling voltage. The value of the voltage gain is unaffected by changes of the thermal voltage.

Abstract: A low pass filter includes a differential amplifier including a positive input end, a negative input end, a positive output end, and a negative output end. A first resistive device is coupled between the negative input end and a first node. A second resistive device is coupled between the positive input end and the first node. A third resistive device substantially the same as the second resistive device is coupled between the negative input end and a second node. A fourth resistive device substantially the same as the first resistive device is coupled between the positive input end and the second node. A first capacitive device is coupled between the negative input end and the positive output end. Finally, a second capacitive device substantially the same as the first capacitive device is coupled between the positive input end and the negative output end.

Abstract: A method of the invention is used for checking a wire layout causing high wire resistance. The method includes the steps of: selecting a first metal layer, a second metal layer and a third metal layer, wherein each of the first and third metal layer includes a power wire for transmitting power, and the second metal layer is adjacent to the first and third metal layers; selecting one region in the second metal layer, wherein the first and the third metal layers have the power wires at positions corresponding to the region and the second metal layer has no wire at the region; and disposing a conductive metal layer coupled to the first and third metal layer in the region for lowering the equivalent wire resistance.

Abstract: A method of the invention is used for checking the via density between two adjacent layers of an IC layout. The method includes selecting a first metal layer and a second metal layer, wherein the first metal layer is adjacent to the second one, each of the metal layers has at least a wire, and the metal layers are coupled to each other through at least a first via; calculating the cross-sectional area of the first via and the overlapping area of the overlapped part of the wires in the first and the second metal layers; and disposing at least a second via in the overlapped part to couple the first and the second metal layers if the ratio of the cross-sectional area to the overlapping area is smaller than a predetermined ratio value.

Abstract: A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.

Abstract: A variable gain amplifier having a linear decibel-scale gain comprises an amplifying stage for generating an output voltage according to a differential input voltage, and a gain-controlling stage for outputting a gain-controlling voltage to the amplifying stage according to a first controlling voltage and a second controlling voltage. A voltage gain of the variable gain amplifier is inversely proportional to a simple exponential function, and the value of the simple exponential function is determined by the difference between the first controlling voltage and the second controlling voltage.

Abstract: An analog circuit apparatus connected to a high voltage source includes a transistor and an interface unit. The transistor has a low operation voltage smaller than the high voltage source and a breakdown voltage. The interface unit is coupled to the transistor in series for preventing the low operation voltage higher than the breakdown voltage.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: An ESD clamp circuit includes an ESD detecting unit and a discharge circuit with a longitudinal BJT. The longitudinal BJT is formed on a P-type substrate and includes a deep N-well formed on the P-type substrate, a P-well formed on parts of the deep N-well, a N-well formed on the deep N-well surrounding the P-well, a first N+ region formed on parts of the P-well and electrically coupled to a first voltage, a P+ region formed on the P-well surrounding the first N+ region and electrically coupled to a trigger signal, and a second N+ region formed on the N-well and electrically coupled to a second voltage. In the structure of the longitudinal BJT, the leakage current can be decreased, the current gain can be increased, and the dimension of the ESD clamp circuit can be reduced.

Abstract: The invention is to provide a receiving end architecture comprising a variable gain amplifier, for outputting a pair of differential signals comprising a first signal and a second signal via a first and a second outputs respectively according to the receiving signal through adjusting the amplitude of the receiving signal; a mix-type sample-and-hold circuit for outputting a first sampled signal via a first end and a second sampled signal via a second end and then outputting the second sampled signal via the first end and the first sampled signal via the second end through performing sample-and-hold on the pair of differential signals; and an analog/digital converter coupled to the mix-type sample-and-hold circuit for generating a digital signal according to the first and the second sampled signals.

Abstract: A symmetric electrical connection system for balancing impedance between a first node and a third node and impedance between a second node and a fourth node. The system includes a first conducting wire, a third conducting wire, a fifth conducting wire, and a seventh conducting wire all installed in a first layer. The system further includes a second conducting wire, a fourth conducting wire, a sixth conducting wire, and an eighth conducting wire all installed in a second layer. The first conducting wire and the eighth conducting wire are crossed but electrically insulated. The second conducting wire and the third conducting wire are crossed but electrically insulated. The fourth conducting wire and the fifth conducting wire are crossed but electrically insulated. The sixth conducting wire and the seventh conducting wire are crossed but electrically insulated. In a preferred embodiment, the appearances and the materials of the conducting wires are essentially equivalent.

Abstract: An impedance circuit for providing an equivalent impedance between a first node and a second node includes a first impedance for providing a first impedance value, a first switch element electrically connected to the first impedance, a second impedance for providing a second impedance value, and a second switch element electrically connected to the second impedance. The equivalent impedance is determined by the first impedance value and the second impedance value, and by controlling the turn on time and the turn off time of the first switch element and the second switch element.

Abstract: An AFE device with adjustable bandwidth filtering functions includes an input buffer and an ADC, and the adjustable bandwidth filtering functions may be integrated in the ADC or the input buffer. When they are integrated in the ADC, a capacitor and a switch module in the ADC may implement the functions, wherein the capacitor originally samples and holds analog signals. The switch module includes a plurality of transistor switches connected in parallel, and one (or multiple ones connected in parallel) of the transistor switches may be selected, according to a selection code, as an equivalent resistor to be serially connected to the capacitor to form a filter circuit. The selection code may be a one-of-N code or a thermometer code.