Abstract: The variable gain amplifier of the present invention includes at least an operation amplifier. By choosing one of output stages, a feedback resistor is selected and the gain of the variable gain amplifier is decided according to the resistance of the selected feedback resistor, as desired. By adjusting the gain of the variable gain amplifier, the received signals can be amplified or attenuated in accordance with design requirement. The variable gain amplifier can include a two-stage architecture, in which a first stage is used for coarse gain adjustment and a second stage is used for fine gain adjustment. The gain of the two-stage variable gain amplifier can be easily adjusted to a desired value.

Abstract: The present invention discloses an impedance matching circuit which is suitable to be applied on an IC chip. The impedance matching circuit comprises a resistor unit, an OP amplifier circuit connected with the resistor unit, a feedback selecting circuit connected in parallel with the OP amplifier circuit, and a resistor selecting circuit connected with both the OP amplifier circuit and the feedback selecting circuit. The feedback selecting circuit further includes a plurality of switching circuits for enabling some of the resistors furnished in the resistor selecting circuit. By selecting and actuating one of the switching circuits, some certain resistors will be enabled so as to adjust the resistance value of the resistor selecting circuit. The resistor unit and the switching circuits are designed in such a manner that the resistor unit is able to compensate an equivalent resistance of the switching circuit which is actuated.

Abstract: A filter circuit of the present invention provides a transconductance device for outputting a current signal according to an input voltage and a feedback voltage; a transresistance device coupled to the transconductance device for outputting a output voltage according to the current signal; and a feedback device coupled between the transconductance device and the transresistance device for outputting the feedback voltage according to the output voltage. The transresistance device is coupled to the transconductance device via a resistor network comprising a plurality of stages connected serially, wherein each stage of the resistor network comprises: an input node; an output node; a first resistor coupled between the input node and the ground; and a second resistor coupled between the input node and the output node.

Abstract: An amplifier circuit having a high time constant. An operational amplifier includes a non-converting input terminal coupled to a ground, a converting input terminal and an output terminal. A first resistor network including at least one stage is coupled between the converting input terminal and the output terminal. Each stage of the first resistor network includes a first node, a first current path and a second current path connected to the first node. The first current path of each stage of the first resistor network is connected to the first node of the next stage, the second current path of each stage of the first resistor network is grounded, and the first current path of the first stage of the first resistor network is connected to the converting input terminal. A loading unit is coupled between the converting input terminal and the output terminal.

Abstract: An image processing device includes a peripheral circuit and an AFE device. The peripheral circuit is coupled to a display card, and the display signals may be inputted to the AFE device, which processes the display signals, via the peripheral circuit. The image signals outputted from the display card are single-ended analog signals including a red signal, a green signal and a blue signal. The AFE device receives the signals and then utilizes its red, green and blue converters to convert the signals into digital ones. It is to be noted that the red, green, and blue converters share the same ground, which is electrically connected to another ground of the peripheral circuit. Thus, the peripheral circuit and the AFE device have the same reference ground level so as to avoid the distortion caused when the image signals are converted from single-ended ones into the differential ones.

Abstract: An amplifying circuit includes a differential amplifier having a positive input end, a negative input end, a positive output end, and a negative output end; a first input impedance coupled between the negative input end and a first input signal; a second input impedance coupled between the positive input end and the first input signal; a third input impedance coupled between the negative input end and a second input signal; a fourth input impedance coupled between the positive input end and the second input signal; a first output impedance coupled between the negative input end and the positive output end; a second output impedance coupled between the negative input end and the negative output end; a third output impedance coupled between the positive input end and the positive output end; and a fourth output impedance coupled between the positive input end and the negative output end.

Abstract: An audio processing system for used in a multi-channel audio chip includes a multiplexer, a digital-to-analog converter, a de-multiplexer, a controller and N sample-and-hold circuits. The multiplexer receives N digital signals and outputs the digital signals one by one in a time-division manner. The digital-to-analog converter receives the digital signals from the multiplexer and converts them into corresponding N analog signals. The de-multiplexer outputs the analog signals one by one in a time-division manner. The controller generates control signals to control the selection of the multiplexer and the de-multiplexer. The sample-and-hold circuits hold the analog signals for a predetermined period of time and then outputs the signals, respectively.

Abstract: The line driver with active termination includes: a differential amplifier having an inverting output terminal, a non-inverting output terminal, an inverting input terminal, and a non-inverting input terminal; a first resistor unit coupled to the inverting input terminal; a impedance matching resistor unit coupled to the non-inverting output terminal; and a resistive feedback network, having a plurality of resistors in symmetric configuration. The resistive feedback network further includes: a second resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; a third resistor unit coupled to the non-inverting output terminal and the inverting input terminal; a fourth resistor unit coupled to the impedance matching resistor unit and the inverting input terminal; and a fifth resistor unit coupled to the inverting output terminal and the inverting input terminal.

Abstract: The present invention discloses an impedance matching circuit which is suitable to be applied on an IC chip. The impedance matching circuit comprises a resistor unit, an OP amplifier circuit connected with the resistor unit, a feedback selecting circuit connected in parallel with the OP amplifier circuit, and a resistor selecting circuit connected with both the OP amplifier circuit and the feedback selecting circuit. The feedback selecting circuit further includes a plurality of switching circuits for enabling some of the resistors furnished in the resistor selecting circuit. By selecting and actuating one of the switching circuits, some certain resistors will be enabled so as to adjust the resistance value of the resistor selecting circuit. The resistor unit and the switching circuits are designed in such a manner that the resistor unit is able to compensate an equivalent resistance of the switching circuit which is actuated.

Abstract: The present invention generally relates to a generator and a method for generating a recovered clock with high phase resolution. The recovered clock generator comprises a multi-phase clock generator to generate a plurality of multi-phase clock signals with a predetermined frequency higher than a target frequency; a phase selector for receiving the multi-phase clock signals and outputting a selected-phase clock signal according to a selecting signal; and a frequency divider for dividing the frequency of the selected-phase clock signal so as to generate a recovered clock with the target frequency. The recovered clock generator further comprises a phase interpolation unit between the multi-phase clock generator and phase selector. Therefore, the recovered clock generator of the invention can be implemented with less circuit space, and the wires of the layout will not interference the accuracy and the monotonic of the selected clock.

Abstract: A fast start-up low-voltage bandgap voltage reference circuit is proposed. The bandgap voltage reference circuit comprises: a first current generator, which is implemented by a self-bias unit and a current mirror for generating a first reference current with positive temperature coefficient; a second current generator, which is connected to a point with negative temperature coefficient in the first current generator to generate a second reference current with negative temperature coefficient; and a resister for converting the first reference current and the second reference current into a low-voltage bandgap voltage independent of temperature. Because the bandgap voltage reference circuit of the invention uses the resistor to convert the first reference current and the second reference current into voltage, the circuit can provide low-voltage bandgap voltage.

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract: The present invention discloses an impedance matching circuit with automatic adjustment and a method thereof. The impedance matching circuit comprises: a resistor, for receiving a reference voltage and generating a reference current; a detection unit, for detecting resistance variation and generating a plurality of comparison voltages according to said reference current; a comparison unit, for comparing said reference voltage with said comparison voltages, and generating a control signal; and a composite resistor unit, for receiving said control signal and generating a matched impedance. Therefore, a matched impedance value can be obtained within a designed range in despite of the manufacturing process and the operation environment.

Abstract: The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

Abstract: A receiver with baseline wander correction for correcting a received input signal. The receiver includes first and second biasing resistor networks configured to receive first and a second signal of the received input signal, and to produce a first correction signal and a second correction signal. A comparator is employed to compare the first and the second correction signals in order to produce a control signal. The receiver also has comparison logic and compensation control circuitry. The comparison logic generates a logic signal according to the first and the second correction signals. Finally, the compensation control circuitry produces a compensation signal and provides it to respective output terminals of the first and the second biasing resistor networks so as to correct respective DC values of the first and the second correction signals.

Abstract: The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract: An audio converting device including a digital high-pass filter, an expander, a digital low-pass filter, a delta-sigma modulator, a digital-to-analog converter, an analog low-pass filter and a gain control unit is provided. The digital high-pass filter in this invention can filter out a direct-current component of digital audio data such that the production of noise is avoided when the volume is adjusted by users.

Abstract: A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.

Abstract: A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.