Patents by Inventor Chao-Chieh Li

Chao-Chieh Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296101
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh LI, Hao-chieh CHAN
  • Publication number: 20190267944
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Patent number: 10295583
    Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen
  • Patent number: 10291179
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10270487
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the modulation frequency is higher than a frequency of the reference clock; a reference phase generating unit arranged for generating a reference phase according to the reference clock, the modulation clock, the first FCW, the second FCW, and the third FCW; a digital-controlled oscillator (DCO) arranged for to generating the oscillator clock according to the reference phase. An associated method is also disclosed.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Publication number: 20190068242
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the modulation frequency is higher than a frequency of the reference clock; a reference phase generating unit arranged for generating a reference phase according to the reference clock, the modulation clock, the first FCW, the second FCW, and the third FCW; a digital-controlled oscillator (DCO) arranged for to generating the oscillator clock according to the reference phase. An associated method is also disclosed.
    Type: Application
    Filed: January 26, 2018
    Publication date: February 28, 2019
    Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Publication number: 20190068201
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 28, 2019
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Publication number: 20190068199
    Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 28, 2019
    Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Robert Bogdan Staszewski
  • Publication number: 20190068206
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Application
    Filed: January 24, 2018
    Publication date: February 28, 2019
    Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Patent number: 10121781
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20180152139
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Application
    Filed: December 20, 2016
    Publication date: May 31, 2018
    Inventors: CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Patent number: 9748241
    Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ruey-Bin Sheen, Chao-Chieh Li, Ying-Yu Hsu
  • Publication number: 20170179216
    Abstract: According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor.
    Type: Application
    Filed: May 10, 2016
    Publication date: June 22, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao Chieh LI, Hao-chieh CHAN
  • Patent number: 9685433
    Abstract: In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chao-Chieh Li
  • Publication number: 20170154876
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 1, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 9595474
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 9531396
    Abstract: A device is disclosed that includes an oscillator, a frequency detector, and a selection circuit. The oscillator is configured to generate an oscillating signal. The oscillator includes a first tuning bank and a second tuning bank. The first tuning bank is configured to adjust the frequency of the oscillating signal within a first frequency band. The second tuning bank is configured to adjust the frequency of the oscillating signal within a second frequency band. The frequency detector is configured to generate a control signal according to at least one signal indicating the frequency of the oscillating signal. The selection circuit is configured to activate at least one of the first tuning bank and the second tuning bank according to the control signal.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chao-Chieh Li
  • Publication number: 20160305999
    Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN
  • Publication number: 20160254260
    Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: RUEY-BIN SHEEN, CHAO-CHIEH LI, YING-YU HSU
  • Patent number: 9165925
    Abstract: Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao-Chieh Li, Shyh-An Chi, Ruey-Bin Sheen, Chih-Hsien Chang