Patents by Inventor Chao-Chieh Li

Chao-Chieh Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150243643
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Application
    Filed: May 8, 2015
    Publication date: August 27, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 9035464
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Publication number: 20150084107
    Abstract: In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 26, 2015
    Inventor: CHAO-CHIEH LI
  • Publication number: 20150061782
    Abstract: Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHAO-CHIEH LI, SHYH-AN CHI, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
  • Publication number: 20150061148
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh LI, Ruey-Bin SHEEN, Chih-Hsien CHANG
  • Patent number: 8832623
    Abstract: Among other things, one or more techniques and systems for generating a common design rule check (DRC) rule set for verification of a design layout and for generating a common dummy insertion utility for design layout processing are provided. That is, the common DRC rule set comprises a set of design rules having design rule constraint values corresponding to a restriction threshold, such as a most restrictive value. The common dummy insertion utility is used to insert dummy polygons into a design layout according to a dummy size constraint and a dummy spacing constraint. The design layout is verified as compliant with the common DRC rule set. Once verified, the design layout can be converted from a universal design layout format to a target metal scheme to create a transformed design layout. In this way, design layouts, formatted according to the universal design layout, can be transformed to other formats.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Shueh Yuan, Chao-Chieh Li
  • Patent number: 7876165
    Abstract: A ring-based multi-push voltage-controlled oscillator (VCO) generates a multi-push output signal using a control voltage. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by the delay cells is to multiply the frequency of the multi-push output signal to increase the frequency tuning range.
    Type: Grant
    Filed: April 4, 2009
    Date of Patent: January 25, 2011
    Assignee: National Taiwan University
    Inventors: Chao-Chieh Li, Chung-Chun Chen, Huei Wang
  • Publication number: 20100253440
    Abstract: A ring-based multi-push voltage-controlled oscillator (VCO) with the control voltage to generate the multi-push output signal is disclosed. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by delay cells is to multiply the frequency tuning range.
    Type: Application
    Filed: April 4, 2009
    Publication date: October 7, 2010
    Inventors: Chao-Chieh Li, Chung-Chun Chen, Huei Wang