Patents by Inventor Chao-Ching Chang

Chao-Ching Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154025
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal
    Type: Application
    Filed: January 10, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20230378115
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: July 23, 2023
    Publication date: November 23, 2023
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20230369516
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. wherein the composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
  • Patent number: 11756913
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Patent number: 11749760
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Publication number: 20230268367
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Patent number: 11652124
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Wei Huang, Chao-Ching Chang, Yun-Wei Cheng, Chih-Lung Cheng, Yen-Chang Chen, Wen-Jen Tsai, Cheng Han Lin, Yu-Hsun Chih, Sheng-Chan Li, Sheng-Chau Chen
  • Publication number: 20220310544
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20220278242
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
  • Patent number: 11373971
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Patent number: 11335817
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han Lin, Chao-Ching Chang, Yi-Ming Lin, Yen-Ting Chou, Yen-Chang Chen, Sheng-Chan Li, Cheng-Hsien Chou
  • Publication number: 20220115421
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 14, 2022
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Publication number: 20210407947
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Patent number: 11189654
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20210050460
    Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Han LIN, Chao-Ching CHANG, Yi-Ming LIN, Yen-Ting CHOU, Yen-Chang CHEN, Sheng-Chan LI, Cheng-Hsien CHOU
  • Publication number: 20200312894
    Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.
    Type: Application
    Filed: June 14, 2020
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Chih-Hui Huang, Jian-Shin Tsai, Cheng-Yi Wu, Chia-Hsing Chou, Yi-Ming Lin, Min-Hui Lin, Chin-Szu Lee
  • Publication number: 20200115823
    Abstract: A method for preparing hydrophobic fibers by electrospinning of polymer is provided, which may include the following steps: providing a polymer material including poly(methyl methacrylate); providing a solvent including 2-propanol and water; adding the polymer material into the solvent to form a mixed solution; heating and stirring the mixed solution; electrospinning the mixed solution to generate polymer fibers.
    Type: Application
    Filed: August 5, 2019
    Publication date: April 16, 2020
    Inventors: CHAO-CHING CHANG, HUI-YI CHANG, LIAO-PING CHENG