Patents by Inventor Chao-Ching Cheng

Chao-Ching Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11056400
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Publication number: 20210202731
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer.
    Type: Application
    Filed: July 16, 2020
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li CHIANG, Yu-Chao LIN, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung-Ying LEE
  • Patent number: 11043577
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 11043578
    Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee
  • Publication number: 20210184016
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.
    Type: Application
    Filed: January 21, 2021
    Publication date: June 17, 2021
    Inventors: Chao-Ching CHENG, Wei-Sheng YUN, Shao-Ming YU, Tsung-Lin LEE, Chih-Chieh YEH
  • Publication number: 20210184111
    Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 11038044
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11038043
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Publication number: 20210175367
    Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H. Diaz
  • Publication number: 20210159124
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 27, 2021
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Hung-Li CHIANG, Tzu-Chiang CHEN
  • Patent number: 11004965
    Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Chun-Chieh Lu, Ming-Yang Li, Tzu-Chiang Chen
  • Publication number: 20210134945
    Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Li CHIANG, Chao-Ching Cheng, Tzu-Chiang Chen, I-Sheng Chen
  • Publication number: 20210134992
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Application
    Filed: July 12, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Patent number: 10998429
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 10998426
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 10991811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Publication number: 20210119131
    Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Timothy Vasen, Chao-Ching Cheng, Matthias Passlack, Martin Christopher Holland, Tse-An Chen, Lain-Jong Li
  • Patent number: 10964798
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10964817
    Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, Chih-Hsin Ko, Hsingjen Wann
  • Publication number: 20210091229
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Application
    Filed: September 22, 2019
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen