Abstract: The invention provides a scan driving circuit for an oxide semiconductor thin film transistor. The scan driving circuit for an oxide semiconductor thin film transistor includes multiple cascade connected GOA units and a shared auxiliary inverter. Each of the GOA units includes a main inverter. The auxiliary inverter is electrically connected to each main inverter to form corresponding pull-down holding parts for the respective GOA units, which can achieve the sharing of the pull-down holding parts of the multiple stages GOA units, the number of TFT elements can be reduced and therefore GOA layout space as well as circuit power consumption can be reduced.

Abstract: The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (DCL) and setting the constant low voltage level (DCL)<the second negative voltage level (VSS2)<the first negative voltage level (VSS1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS.

Abstract: A pixel driving circuit includes a signal loading component, a storage capacitor, a compensation component, a mirror component, and a drive transistor. In a data transmission stage, the signal loading component transmits a received image data signal to the gate of a drive transistor, which is stored in a storage capacitor; and in a threshold voltage compensation stage, the compensation component connects the gate of the drive transistor to the source of the drive transistor so as to generate a drive signal dependent upon the threshold voltage of the drive transistor from the signal stored in the storage capacitor and to drive an organic light emitting diode to emit light, thus eliminating an influence of the threshold voltage of the drive transistor on the current through the organic light emitting diode and preventing the brightness of the organic light emitting diode from varying over its operating period of time.

Abstract: In the GOA circuit repair method provided by the present invention, the repair signal (Repair signal) is received by the GOA unit circuits of the Nth stage and the N+1th stage via the repair signal line (L1) respectively to be the output signal of the GOA unit circuit of the Nth stage, and the scan control signal of the GOA unit circuit of the N+1th stage to achieve the repair to the GOA unit circuit of the Nth stage; or the start signal (STV) is received by the GOA unit circuits of the N+1th stage and the N+2th stage via the start signal line (L5) respectively to be the output signal of the GOA unit circuit of the N+1th stage, and the scan control signal of the GOA unit circuit of the N+2th stage to achieve the repair to the GOA unit circuit of the N+1th stage, and meanwhile, the repair signal (Repair signal) is received by the GOA unit circuits of the N+2th stage and the N+3th stage via the repair signal line (L1) respectively to be the output signal of the GOA unit circuit of the N+2th stage, and the scan

Abstract: The present invention provides a PMOS gate driving circuit, comprising a plurality of GOA unit circuits which are cascade connected, and the GOA unit circuit of every stage comprises a pull-up controlling module (100), a pull-up module (200), a transmission module (300), a first pull-down module (400), a bootstrap capacitor (500) and a pull-down holding module (600); the pull-up controlling module (100) receives a constant negative voltage level (VSS1), which can reduce the influence of PMOS element leakage to the first node (Q(N)); the pull-down holding module (600) is provided with a dual inverter (F1) comprising P-type thin film transistors, and utilizes special leakage prevention design, which can reduce the leakage of the first node (Q(N)) to prevent the influence of the electrical property of the depletion-mode P-type thin film transistors to the output of the inverter, raise the stability of the gate driving circuit, and promote the integration of the panel.

Abstract: The present invention provides a gate driving circuit applied for 2D-3D signal setting, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part, a pull-down holding part and a pull-up compensation part; on the basis of the gate driving circuit utilizing the present GOA skill, the present invention adds a pull-up compensation part to compensate the leakage gap existing in the 2D signal transmission to ensure that the voltage level of the gate signal point Q(N) will not descend in leakage gap period; by introducing an additional DC control signal source DC to control the activation and deactivation of the pull-up compensation part for activating it in 2D mode to realize co

Abstract: A GOA circuit applied to a liquid crystal display is disclosed, which comprises a plurality of cascaded shift register units, an (N)th level shift register unit is controlled to charge an (N)th level scanning line accordingly. The (N)th level shift register unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, a down transfer circuit, and an bootstrap capacitor, and a display device is also disclosed herein. By replacing scanning lines with a constant voltage VDD or two voltages to accomplish the function of down transfer, the loading of scanning lines and the risk which comes with wiring step-by-step are decreased, forward-scanning operation and backward-scanning operation are accomplished accordingly.

Abstract: A gate-drive-on-array circuit for use with oxide semiconductor thin-film transistors of the present invention uses two constant-voltage negative potential sources (VSS1, VSS2) that are reduced step by step and low potentials of a high-frequency clock signal (CK(n)) and a low-frequency clock signal (LC1, LC2) to ensure an up-pull circuit portion (200) is maintained in a well closed condition during a non-operating period without being affected by the high-frequency clock signal (CK(n)) so as to ensure the circuit operates normally. Further, the first down-pull circuit portion (400) is re-designed to prevent influence thereof imposed on the outputs of the first node (Q(N)) and the output terminal (G(N)) so as to ensure the first node (Q(N)) and the output terminal (G(N)) can supply the outputs normally without generating signal distortion.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a first DC low voltage VSS1 and a second DC low voltage VSS2; the pull-down holding part comprises a first pull-down holding part and a second pul

Abstract: A scan driving circuit and a liquid crystal display device include a pull-up assembly, a pull-up control assembly that drives the pull-up assembly, a pull-down maintaining assembly, a reference low-level signal, and a down-transmitting assembly. A control end of the down-transmitting assembly is coupled to an output end of the pull-up control assembly and a control end of the pull-up assembly, and a current down-transmitting signal is output from an output end of the down-transmitting assembly.

Abstract: A scan driving circuit includes a pull-up assembly, a pull-up control assembly that drives the pull-up assembly, a pull-down maintaining assembly, and a reference low-level signal. The reference low-level signal includes a first reference low-level signal and a second reference low-level signal. When the current scanning line is inactive, the pull-down maintaining assembly controls the reference low-level to be sent to the current scanning line and the output end of the pull-up control assembly according to a pull-down maintaining signal.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a first DC low voltage VSS1.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS; the pull-down holding part comprises a first pull-down holding part and a second pull-down holding part to alternately work.

Abstract: The present invention provides a gate driving circuit applied for 2D-3D signal setting, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part, a pull-down holding part and a pull-up compensation part; on the basis of the gate driving circuit utilizing the present GOA skill, the present invention adds a pull-up compensation part to compensate the leakage gap existing in the 2D signal transmission to ensure that the voltage level of the gate signal point Q(N) will not descend in leakage gap period; by introducing an additional DC control signal source DC to control the activation and deactivation of the pull-up compensation part for activating it in 2D mode to realize co

Abstract: A gate driver on array (GOA) circuit for an LCD includes multiple cascaded GOA units. A Nth stage GOA unit controls a charging of a Nth stage horizontal scanning line. The Nth stage GOA unit includes a pull-up circuit, a pull-down circuit, a first pull-down holding circuit, a second pull-down holding circuit, a bridge circuit, a pull-up control circuit, a transfer circuit, and a boast capacitor. A seventh TFT connects in parallel with a third TFT of the first pull-down holding circuit. A fourteenth TFT connects in parallel with a tenth TFT of the second pull-down holding circuit. The gate of the seventh TFT and the gate of the fourteenth TFT are connected, and both connected to a starting signal from (N?1)th GOA unit or a (N?1)th stage horizontal scanning line. An LCD device also uses the GOA circuit to reduce the delay of the gate signal output.

Abstract: A scan driving circuit includes a pull-up assembly, a pull-up control assembly that drives the pull-up assembly, a pull-down maintaining assembly, and a reference low-level signal. When the current scanning line is inactive, the pull-down maintaining assembly is controlled by a pull-down maintaining signal to make a reference low-level signal be sent to an output end of the pull-up control assembly and the current scanning line.

Abstract: A gate driver on array (GOA) circuit for an LCD includes multiple cascaded GOA units. A Nth stage GOA unit controls a charging of a Nth stage horizontal scanning line. The Nth stage GOA unit includes a pull-up circuit, a pull-down circuit, a first pull-down holding circuit, a second pull-down holding circuit, a bridge circuit, a pull-up control circuit, a transfer circuit, and a boast capacitor. A seventh TFT connects in parallel with a third TFT of the first pull-down holding circuit. A fourteenth TFT connects in parallel with a tenth TFT of the second pull-down holding circuit. The gate of the seventh TFT and the gate of the fourteenth TFT are connected, and both connected to a starting signal from (N?1)th GOA unit or a (N?1)th stage horizontal scanning line. An LCD device also uses the GOA circuit to reduce the delay of the gate signal output.

Abstract: A driving circuit and a liquid crystal display apparatus having the same are disclosed. The driving circuit includes a first clock-signal driving circuit, a second clock-signal driving circuit, a data-line driving circuit, and a scanning-line driving circuit. The driving circuit and the liquid crystal display apparatus having the same prevent the delay of primary scanning signals so as to solve a technical problem where conventional liquid crystal display apparatus display images with a low display quality due to the delay of primary scanning signals.

Abstract: The present invention provides a self-compensating gate driving circuit, comprising: a plurality of GOA units which are cascade connected, and a Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit controls charge to a Nth horizontal scanning line G(n) in a display area, and the Nth GOA unit comprises a pull-up controlling part, a pull-up part, a transmission part, a first pull-down part, a bootstrap capacitor part and a pull-down holding part; the pull-up part, the first pull-down part, the bootstrap capacitor part and the pull-down holding circuit are respectively coupled to a Nth gate signal point Q(N) and the Nth horizontal scanning line G(n), and the pull-up controlling part and the transmission part are respectively coupled to the Nth gate signal point Q(N), and the pull-down holding part is inputted with a DC low voltage VSS.