Patents by Inventor Chao-Hsiang Yang
Chao-Hsiang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10175294Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.Type: GrantFiled: April 7, 2017Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Publication number: 20180204828Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.Type: ApplicationFiled: October 5, 2017Publication date: July 19, 2018Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Publication number: 20170212167Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Patent number: 9618572Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.Type: GrantFiled: June 1, 2016Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Publication number: 20160274183Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.Type: ApplicationFiled: June 1, 2016Publication date: September 22, 2016Inventors: WEI-CHENG WU, HSIEN-PIN HU, SHANG-YUN HOU, SHIN-PUU JENG, CHEN-HUA YU, CHAO-HSIANG YANG
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Patent number: 9372206Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.Type: GrantFiled: August 24, 2015Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Publication number: 20150362526Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: Wei-Cheng WU, Hsien-Pin HU, Shang-Yun HOU, Shin-Puu JENG, Chen-Hua YU, Chao-Hsiang YANG
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Patent number: 9116203Abstract: A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (?m). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.Type: GrantFiled: July 15, 2014Date of Patent: August 25, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Patent number: 9097860Abstract: A lens assembly includes a lens set which includes a first lens, a second lens, a third lens and a fourth lens arranged in sequence along an optical axis. The first lens has a positive optical power. The second lens has a positive optical power. The third lens has a negative optical power. The fourth lens has a positive optical power, and has an image-side surface, an object-side surface, and a peripheral surface interconnecting the two. At least one of the object-side and image-side surfaces has an inflection point located between the optical axis and the peripheral surface. The lens assembly satisfies 15<HFOV/f<50, in which, HFOV represents one half of a maximum angle of view of the lens assembly, and f represents a focal length thereof.Type: GrantFiled: December 27, 2013Date of Patent: August 4, 2015Assignee: Ability Opto-Electronics Technology Co., LTD.Inventors: Hung-Kuo Yu, Chao-Hsiang Yang
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Patent number: 9001437Abstract: An imaging lens assembly includes first, second and third optical lenses that are arranged sequentially from an object side to an image side along an optical axis, and a constant-aperture diaphragm disposed between the second optical lens and the object side. Each of the first and second optical lenses has a positive refractive power near the optical axis. The third optical lens has a negative refractive power near the optical axis and has an object-side surface and an image-side surface, at least one of which has at least an inflection point. The imaging lens assembly satisfies: 0.55<f/Dg<0.85, in which, f is a focal length of the imaging lens assembly, and Dg is a length of a diagonal line of a maximum viewing angle in an imaging plane.Type: GrantFiled: December 27, 2013Date of Patent: April 7, 2015Assignee: Ability Opto-Electronics Technology Co., Ltd.Inventors: Kuo-Yu Liao, Chen-Hung Tsai, Po-Jui Liao, Chao-Hsiang Yang
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Publication number: 20150062724Abstract: A lens assembly includes a lens set which includes a first lens, a second lens, a third lens and a fourth lens arranged in sequence along an optical axis. The first lens has a positive optical power. The second lens has a positive optical power. The third lens has a negative optical power. The fourth lens has a positive optical power, and has an image-side surface, an object-side surface, and a peripheral surface interconnecting the two. At least one of the object-side and image-side surfaces has an inflection point located between the optical axis and the peripheral surface. The lens assembly satisfies 15<HFOV/f<50, in which, HFOV represents one half of a maximum angle of view of the lens assembly, and f represents a focal length thereof.Type: ApplicationFiled: December 27, 2013Publication date: March 5, 2015Applicant: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Hung-Kuo Yu, Chao-Hsiang Yang
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Publication number: 20140376111Abstract: A wide-angle imaging lens assembly comprises a fixing diaphragm and an optical set including three lenses. An arranging order from an object side to an image side is: a first lens; a second lens; a third lens. Two surfaces of the third lens have at least one inflection point from the optical axis to an end point of the aspheric surfaces. At least one surface of the three lenses are aspheric. The fixing diaphragm is disposed at any position between an object and the second lens. By the concatenation between the lenses and the adapted curvature radius, thickness, interval, refractivity, and Abbe numbers, the assembly attains a big diaphragm with ultra-wide-angle, a shorter height, and a better optical aberration.Type: ApplicationFiled: October 18, 2013Publication date: December 25, 2014Applicant: Ability Opto-Electronics Technology Co., Ltd.Inventors: Kuo-yu LIAO, Chao-Hsiang YANG
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Publication number: 20140334018Abstract: An imaging lens assembly includes first, second and third optical lenses that are arranged sequentially from an object side to an image side along an optical axis, and a constant-aperture diaphragm disposed between the second optical lens and the object side. Each of the first and second optical lenses has a positive refractive power near the optical axis. The third optical lens has a negative refractive power near the optical axis and has an object-side surface and an image-side surface, at least one of which has at least an inflection point. The imaging lens assembly satisfies: 0.55<f/Dg<0.85, in which, f is a focal length of the imaging lens assembly, and Dg is a length of a diagonal line of a maximum viewing angle in an imaging plane.Type: ApplicationFiled: December 27, 2013Publication date: November 13, 2014Applicant: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.Inventors: Kuo-Yu Liao, Chen-Hung Tsai, Po-Jui Liao, Chao-Hsiang Yang
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Publication number: 20140327464Abstract: A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (?m). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.Type: ApplicationFiled: July 15, 2014Publication date: November 6, 2014Inventors: Wei-Cheng WU, Hsien-Pin HU, Shang-Yun HOU, Shin-Puu JENG, Chen-Hua YU, Chao-Hsiang YANG
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Patent number: 8797057Abstract: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 ?m. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.Type: GrantFiled: February 11, 2011Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Publication number: 20140043697Abstract: A thin imaging lens assembly with four lenses, having one defined as an object side and an opposite end defined as an image side, and comprising: a lens set, including a first lens, a second lens, a third lens, and a fourth lens that are arranged from the object side to the image side in sequence so as to form an optical structure; and a fixed aperture, deposited between the object side and the image side, wherein the first lens has a positive refractive power around an optical axis thereof; the second lens has a negative refractive power around an optical axis thereof; the third lens has a positive refractive power around an optical axis thereof; and the fourth lens comprises a seventh surface, a convex surface around an optical axis thereof, and an eighth surface, a wavy and concave surface around an optical axis thereof.Type: ApplicationFiled: July 2, 2013Publication date: February 13, 2014Applicant: Ability opto-electronics technology co., ltdInventors: Kuo-Yu LIAO, Chao Hsiang Yang
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Patent number: 8576502Abstract: A miniaturized lens assembly includes a first lens, a stop, a second lens, a third lens, a fourth lens and a fifth lens, all of which are arranged in sequence from an object side to an image side along an optical axis. The first lens is made of plastic material, is a meniscus lens with negative refractive power, and includes a convex surface facing the object side. The second lens is made of plastic material and is a biconvex lens with positive refractive power. The third lens is made of glass material and is a biconvex lens with positive refractive power. The fourth lens is made of glass material, is a biconcave lens with negative refractive power, and is adhered to the third lens to form a compound lens. The fifth lens is made of plastic material, is provided with positive refractive power, and includes an aspheric surface.Type: GrantFiled: July 4, 2012Date of Patent: November 5, 2013Assignee: Asia Optical Co. Inc.Inventors: Chun-Hong Chen, Chao-Hsiang Yang
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Publication number: 20130010375Abstract: A miniaturized lens assembly includes a first lens, a stop, a second lens, a third lens, a fourth lens and a fifth lens, all of which are arranged in sequence from an object side to an image side along an optical axis. The first lens is made of plastic material, is a meniscus lens with negative refractive power, and includes a convex surface facing the object side. The second lens is made of plastic material and is a biconvex lens with positive refractive power. The third lens is made of glass material and is a biconvex lens with positive refractive power. The fourth lens is made of glass material, is a biconcave lens with negative refractive power, and is adhered to the third lens to form a compound lens. The fifth lens is made of plastic material, is provided with positive refractive power, and includes an aspheric surface.Type: ApplicationFiled: July 4, 2012Publication date: January 10, 2013Applicant: ASIA OPTICAL CO. INC.Inventors: Chun-Hong Chen, Chao-Hsiang Yang
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Publication number: 20120206160Abstract: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 ?m. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Cheng WU, Hsien-Pin HU, Shang-Yun HOU, Shin-Puu JENG, Chen-Hua YU, Chao-Hsiang YANG
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Patent number: 8049323Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.Type: GrantFiled: February 16, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Shien Chen, Chao-Hsiang Yang, Jimmy Liang, Han-Liang Tseng, Mirng-Ji Lii, Tjandra Winata Karta, Hua-Shu Wu